• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.5
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• pp.859-865
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• 2013

Esmbedded devices such as smart cards and electronic passports highly demand security of sensitive data. So, the secure implementation of the cryptographic system against various side-channel attacks are becoming more important. In particular, the fault injection attack is one of the threats to the cryptosystem and can destroy the whole system only with single pair of the plain and cipher texts. Therefore, the implementors must consider seriously the attack. Several techniques for preventing fault injection attacks were introduced to a variety of the cryptosystem, But the countermeasures are still inefficient to be applied to the classical RSA cryptosystem. This paper introduces an efficient countermeasure against the fault injection attack for the classical RSA cryptosystem, which is based on the famous Fermat's theorem. The proposed countermeasure has the advantage that it has less computational overhead, compared with the previous countermeasures.

• Journal for History of Mathematics
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• v.19 no.3
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• pp.85-94
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• 2006

We review Galois rings and permutation polynomials over Galois rings with emphasis on cryptological properties of Dickson polynomials and conclude that it is not plausible to obtain the Dickson scheme which has a Galois ring as a plaintext space.

• Review of KIISC
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• v.8 no.4
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• pp.15-46
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• 1998

본 고에서는 큰 수의 인수분해가 어렵다는 사실에 기반한 암호방식인 RSA암호시스템의 안전성에 영향을 미치는 여러 요소에 대하여 고찰하였다. 먼저 RSA시스템에 대하여 간단하게 살펴보고, 다음으로 모듈러 n의 인수분해를 통한 공격 방식을 살펴본다. 그리고 마지막으로 RSA시스템에 대한 공격 방식을 homomorphic공격과 다항식 공격으로 나누어 살펴본다.

• Journal of IKEEE
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• v.22 no.3
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• pp.522-531
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• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• The Journal of Information Technology
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• v.3 no.1
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• pp.61-72
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• 2000

In this paper, we propose a bit-sliced modular multiplication algorithm and a bit-sliced modular multiplier design meeting the increasing crypto-key size for RSA public key cryptosystem. The proposed bit-sliced modular multiplication algorithm was designed by modifying the Walter's algorithm. The bit-sliced modular multiplier is easy to expand to process large size operands, and can be immediately applied to RSA public key cryptosystem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.353-360
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• 1997

In this paper, we propose a new blocking method in which the size of an encryption block is changed according to the size of a message block. The proposed method can be applied to multisignature scheme with no restrictio of the signing order and a multisignature anc be sent secretly to the receiver through RSA encryption. It causes expansion in block size of a multisignuture, but the length of the expanded bits is not greater than the number of signers regardless fo the bit lengths of RSA moduli.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.4
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• pp.479-488
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• 2016

For a secure communication system, it is necessary to use secure cryptographic algorithms and keys. Modern cryptographic system generates high entropy encryption key through standard key derivation functions. Using recent progress in quantum key distribution(QKD) based on quantum physics, it is expected that we can enhance the security of modern cryptosystem. In this respect, the study on the dual key agreement is required, which combines quantum and modern cryptography. In this paper, we propose two key derivation functions using dual key agreement based on QKD and RSA cryptographic system. Furthermore, we demonstrate several simulations that estimate entropy of derived key so as to support the design rationale of our key derivation functions.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1991.11a
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• pp.204-214
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• 1991

개별통신 및 방송통신시스팀에 적합한 암호방식으로서 동일한 통신시스팀 내에 가입된 모든 이용자의 개별키에 공통으로 대치할 수 있는 마스터키 방식을 적용하였다. 사용된 암호방식으로는 키관리가 편리하고 인중기능이 좋은 RSA 공개키 암호방식을 사용하여 RSA마스터키의 생성법을 제시하고 실제 마스터키를 생성하여 개별암호통신 및 방송암호 통신의 방법을 보였다.