• 대한전기학회논문지
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• 제45권1호
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• pp.14-17
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• 1996

We analyzed the characteristics of a power system with superconducting fault current limiter and showed the possibility of the application of a superconducting fault current limiter to a real power system through manufacturing of and experiment about 220Vrms/100Apeak class superconducting fault current limiter. We experimentally confirmed that the overvoltage of superconducting fault current limiter increased as the rate of current sharing to the limiting coil grew. The fault current could be limited within a few milliseconds when it was applied to a power system in series. Therefore, we could confirm that superconducting fault current limiter was effective in protection of a substation or power plant at short-circuit fault. (author). 7 refs., 7 figs., 2 tabs.

• 청정기술
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• 제23권1호
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• pp.42-53
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• 2017

탈질과 탈황을 동시에 수행하는 과산화수소($H_2O_2$) 수용액 세정탑의 반응효율을 증가시키기 위해 예혼합이 이루어지는 혼합 냉각기(mixing quencher) 영역 내부의 유체유동에 대한 수치해석이 수행되었다. 산업공정에서 상용화되고 있는 세정탑 전단부의 혼합냉각기에서 과산화수소 수용액이 주입되는 노즐의 분사방식은 배기가스와 과산화수소 수용액의 혼합에 중요한 역할을 하며, 혼합냉각기에서의 혼합도는 세정탑 의 효율을 결정하는 중요 요소가 된다. 본 연구에서는 혼합냉각기 내부유체의 농도분포 개선을 목적으로 하여 혼합냉각기 내의 노즐 관의 배열을 조절하거나 노즐 팁 각도를 변경하며 유체혼합을 최적화하였다. 전산해석은 이 냉각기영역의 내부유동 및 각 유체 농도에 대한 RMS (root mean square) 값을 계산하여 내부유체의 혼합도의 개선을 확인하였다. 세부적으로는 노즐 관의 위치를 조절할 때 변경되는 냉각기 영역 후단의 농도 RMS 값을 확인하여 난류형성위치에 따른 최적화된 혼합도를 확인하였으며 기본형상 대비 난류형성방향을 조절하는 목적의 노즐 팁 각도를 증감하여 농도분포의 균질화를 비교하였다. 노즐 관의 배열에 따라 난류형성위치와 그에 따른 유체혼합이 해석되었다. 또한 노즐 팁 각도를 조절하는 경우에는 유동방향과의 각도에 따라, 흐름이 병류와 향류에 따라 혼합도의 최적화를 확인할 수 있었다. 노즐 관의 위치는 0.3 m, 노즐 팁은 병류의 $15^{\circ}$일 때 최적의 조건을 가지며 가장 낮은 RMS 값인 12.4%를 가졌다.

• 대한환경공학회지
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• 제33권5호
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• pp.368-377
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• 2011

소규모의 대기오염 배출원으로부터 질소산화물을 저감하는 방법으로 제안된 패키지형 SCR (selective catalytic reduction) 시스템 내에서 암모니아 농도제어에 관한 연구가 시행되었다. SCR 시스템의 효율은 촉매층의 효율적인 활용에 좌우되며 촉매층의 효율적인 사용은 시스템에 유입되는 배기가스의 유동균일도와 암모니아 농도의 균일도에 의해 좌우된다. 본 연구에서는 주어진 최적의 유동조건에서 SCR 시스템 내에 배치된 AIG 형상과 분사 유량 조정에 따른 암모니아 농도분포를 평가하였다. 기본 유동조건에서 분사구의 각도에 따른 전산해석 결과, 배가스 유동에 대해 동류방향($0^{\circ}$)으로 암모니아를 분사한 경우의 농도분포의 RMS(%) 수치는 약 95.3%, 대향방향인 $120^{\circ}$의 각도를 가지는 경우 90.1%로 파악되어 대향방향으로의 분사가 더 효율적인 것으로 파악되었다. 유동박리영역에서 벗어나도록 분사구의 위치를 변경하고 기초계산에서의 속도분포와 농도분포를 기준으로 환원제 유량을 조정한 결과 RMS(%) 수치를 최대 62.8%까지 하강시키는 효과를 가져왔다. AIG 형상 및 배치구조에 혼합증진의 효과를 정리하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.663-665
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• 2000

We fabricated resistive superconducting fault current limiters (SFCL) based on YBCO thin films grown on 2-inch diameter saphire substrates Two SFCLs with nearly identical properties were connected in series to investigate the simultaneous quench. There was a slight difference in the rate of voltage increase between two SFCL units when they were operated independently. This difference. however, resulted in significantly unbalanced power dissipation between the units. This imbalance was removed by connecting a shunt resistor to an SFCL in parallel. The appropriate values of the shunt resistances were $80{\Omega}$ at $75 V_{rms}$. $100{\Omega}$ at $100 V_{rms}$ and $110{\Omega}$ at $120 V_{rms}$, respectively. Increased power input at high voltages also reduced the initial imbalance in power dissipation. but with increase in film temperature to higher than 200 K.

• ETRI Journal
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• 제46권4호
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2000년도 KIASC Conference 2000 / 2000년도 학술대회 논문집
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• pp.133-135
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• 2000

We fabricated resistive super- conducting fault current limiters (SFCL) based on YBCO thin films grown on a 2" diameter $Al_{2}$O_{3} substrate. The minimum quench current of the current minimum quench current of the current limiting element was about 8 $A_{peak}. This SFCL successfully controlled the fault current below 14.3 $A_{peak} at the voltage of 100$V_{rms}, which is otherwise to increase up to 141$A_{peak}. and the quench completion time is less than 3 msec. The temperature of the current limiting element rose to about 200K in 3 cycles after fault. The SFCL showed reproducible characteristics during hundreds times of repeated experiments.ents.

• Journal of Power Electronics
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• 제17권4호
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• pp.1004-1013
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• 2017

This paper presents an interleaving scheme for parallel-connected power systems to reduce the DC-link current ripple. A paralleled generator system generates current ripple by the Pulse Width Modulation (PWM) of each generator side converter. The current ripple in the DC-link degrades the efficiency of the whole generator system and decreases the lifetime of the DC-link capacitors. To mitigate these issues, the expression of the DC-link current is derived by a double-integral Fourier analysis while considering the modulation schemes. Optimized interleaving angles for the parallel generator system are obtained based on an analysis to minimize the dominant current harmonics component. Finally, the proposed interleaving scheme reduces the RMS value of the DC-link current ripple. Simulation and experimental results verify the effectiveness of the proposed interleaving scheme.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.506-511
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• 1998

This paper gives and analytical expression of the average and rms currents of switching devices in volt-age-fed PWM inverters. It is shown that the device currents are represented by a function of the power factor of the load and the normalized output voltage of the inverter. The validity of the derived formulas is confirmed with simulation and experiment, showing that the modulation method has a minor effect on the characteristics of the device current.

• 전기학회논문지
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• 제57권3호
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• pp.494-500
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• 2008

This paper presents the analyzed result of the series arc fault current by using the discrete wavelet transform. The series arcing is caused by a loose connection in series with the load circuit. The series arc current is limited to a moderate value by the resistance of the device connected to the circuit, such as an appliance or a lighting system. The amount of energy in the sparks from the series arcing is less than in the case of parallel arcing but only a few amps are enough to be a fire hazard. Therefore, it is hard to detect the distinctive difference between a normal current and a intermittent arc current. This paper, presents the variation of the ratio of peak values and RMS values of the series arc fault current, and proposes the novel series arc fault detecting method by using the discrete wavelet transform. Loads such as a CFL lamp, a vacuum cleaner, a personal computer, and a television, which has the very similar normal current with the arc current, were selected to confirm the novel method.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2004년도 춘계학술대회 논문집
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• pp.1422-1424
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• 2004

Various deterioration diagnostic techniques and devices are suggested, and most of which measure leakage current components as an indicator of arrester ageing. However, the techniques based on the magnitude of leakage current measure simply RMS or peak value of leakage current components and do not provide detailed information needed in the diagnosis. In this study, we found that the phase vs. wave height of total leakage current is changed or a new wave height is produced with arrester ageing. To complete the new technique, we designed an arrester diagnostic device which is composed of a current detection circuit, an optical transmission circuit, and an analysis program. After measurement of the total leakage current, magnitudes, phase vs. wave height, and harmonics of the leakage current components are analyzed by the microprocessor based device. From the experimental results, we confirmed that the device can measure most parameters needed for the arrester diagnostics and analyze an initial deterioration state.