• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.9-11
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• 2021

최근 임베디드 엣지 컴퓨팅 디바이스에서 AI와 같은 인공지은 연산을 수행하여 AI 추론 연산의 가속화 및 분산화가 많이 이루어지고 있다. 엣지 디바이스는 임베디드 프로세서를 기반으로 AI의 가속 연산을 위해서 내부에 딥러닝 가속기를 포함하여 가속화시키는 시스템 구성을 하고 있다. 딥러닝 가속기는 복잡한 Neural Network 연산을 위한 데이터 이동이 많으며 외부 메모리와 내부 딥러닝 가속기간의 효율적인 데이터 이동 및 버퍼링이 필요하다. 본 연구에서는 엣지 디바이스 딥러닝 가속기 내부의 버퍼 구조를 모델링하고, 버퍼의 크기에 따른 버퍼링 효과를 분석해 보았다. 딥러닝 가속기 버퍼 구조는 RISC-V 프로세서 기반 가상 플랫폼에 구현되었다. 이를 통해서 딥러닝 모델에 따른 딥러닝 가속기 버퍼의 사용성을 분석할 수 있다.

• ETRI Journal
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• v.10 no.3
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• pp.24-35
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• 1988

본 논문은 한국전자통신연구소에서 개발하고 있는 RISC 형태의 32비트 프로세서인 HARP(High-performance Architecture for Risc-type Processor)의 파이프라인 설계와 익셉션 처리 방법에 관한 것이다. HARP의 파이프라인은 명렁어 페치의 병목현상을 해결하기 위하여 중첩된 메모리 액세스 방법을 사용하며 이는 5단계로 구성된다. 그리고 명령어 동시 수행으로 인해 발생하는 자원 충돌을 해결하기 위하여 bypassing logic, instruction fetch unit 및 code-reorganizer를 사용한다. 명령어 수행시 파이프라인 상에서 발생하는 익셉션에 대해서는 익셉션 처리의 복잡성을 피하기 위하여 instruction restart 방법을 사용한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.609-612
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• 2002

본 논문은 다양한 멀티미디어 응용을 위한 재구성가능(reconfigurable) 구조의 프로세서 설계에 대해서 연구하였다. 설계된 프로세서는 RISC 코어 프로세서와 코스-그레인(coarse-grain) 구조의 재구성가능 셀들의 배열로 이루어진 처리 유닛으로 구성되었다. 여기서 사용된 RISC 코어 프로세서는 하드웨어 구조를 간단히 하기 위하여 MIPS 명령어들 중에서 사용빈도가 높은 것들만 고려하였으며, 재구성가능 처리를 위한 별도의 명령어를 추가하였다. 본 논문에서 제시한 재구성가능 프로세서는 VHDL로 모델링하여 실행을 검증하였으며, 하드웨어의 유연성을 증가하여 다양한 멀티미디어 응용에 적용함과 아울러 속도향상에 기여함을 볼 수 있었다.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.11
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• pp.229-232
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• 1995

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.937-949
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• 1988

This paper proposes a code optimization algorithm for dealing with hazards which are occurred in pipelined architecture due to resource dependence between executed instructions. This algorithm solves timing hazard which results from resource conflict between concurrently executing instructions, and sequencing hazard due to the delay time for branch target decision by reconstructing of instruction sequence without pipeline interlock. The reconstructed codes can be generated efficiently by considering timing hazard and sequencing hazard simultaneously. And dynamic execution time of program is improved by considering structral hazard which can be existed when pipeline is controlled dynamically.

• 전기의세계
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• v.37 no.8
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• pp.12-16
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• 1988

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.974-984
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• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.7
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• pp.144-149
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• 2002

This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.