• Title/Summary/Keyword: RF frontend

Search Result 7, Processing Time 0.019 seconds

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

  • Rastegar, Habib;Ryu, Jee-Youl
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.16 no.5
    • /
    • pp.595-604
    • /
    • 2016
  • Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

RF Band-Pass Sampling Frontend for Multiband Access CR/SDR Receiver

  • Kim, Hyung-Jung;Kim, Jin-Up;Kim, Jae-Hyung;Wang, Hongmei;Lee, In-Sung
    • ETRI Journal
    • /
    • v.32 no.2
    • /
    • pp.214-221
    • /
    • 2010
  • Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

Trends on Development of Software Radio Platform for Mobile Communications (이동통신 소프트웨어 라디오 플랫폼 개발동향)

  • Park, C.;Lee, S.Q.;Kim, J.U.;Kim, I.G.
    • Electronics and Telecommunications Trends
    • /
    • v.31 no.6
    • /
    • pp.107-115
    • /
    • 2016
  • 소프트웨어 기반의 이동통신 시스템 개발 기술 즉, 소프트웨어를 이용하여 재구성이 가능한 이동통신 시스템 개발 기술이 연구되어 왔다. 최근에는 소프트웨어 기반 이동 통신 시스템 개발에 가상화 기술이 적용된 가상화 기반의 이동통신 플랫폼 개발 기술에 대한 연구가 활발히 진행되고 있다. 가상화 기반 이동통신 플랫폼 개발 기술은 소프트웨어를 이용하여 범용 하드웨어 컴퓨팅 플랫폼상에서 무선 접속 기능, 프로토콜 처리 기능 및 RF/IF 신호처리 기능의 구현이 가능할 뿐만 아니라, 가상화 플랫폼을 통하여 다양한 무선 접속 규격 수용 및 유연한 시스템 자원 활용이 가능한 기술이다. 본고에서는 가상화 기반의 이동통신 플랫폼 개발 기술에 대해 간략히 소개하고, 소프트웨어 기반 이동통신 플랫폼 개발 현황 및 가상화 기반의 이동통신 시스템 플랫폼에서 소프트웨어를 통해 RF 신호처리 기능을 용이하게 하는 상용 소프트웨어 RF 플랫폼 즉, Software Radio Frontend의 개발 동향에 대해 살펴보고자 한다.

  • PDF

TDD Communication System Architecture implementing Digital Predistortion scheme (DPD를 적용한 TDD 방식의 통신 시스템 구조)

  • Kim, Jeong-Hwi;Ryoo, Kyoo-Tae
    • Proceedings of the IEEK Conference
    • /
    • 2008.06a
    • /
    • pp.181-182
    • /
    • 2008
  • In this paper, an cost-effective system architecture is proposed to implement digital predistortion scheme for linearizing the PA amplifing TDD wideband signal. To make digital predistorted signal for compensating nonlinearity of PA, a dedicated ADC and a frequency-down converter are necessary. Proposed scheme is based on the TDD feature that the RF receiver frontend is idle state during the downlink signal processing time and utilize them to make the digital predistorted signal for PA.

  • PDF

Implementation and Experimental Test Result of a Multi-frequency and Multi-constellation GNSS Software Receiver Using Commercial API

  • Han, Jin-Su;Won, Jong-Hoon
    • Journal of Positioning, Navigation, and Timing
    • /
    • v.8 no.1
    • /
    • pp.1-12
    • /
    • 2019
  • In this paper, we implement a navigation software of a Global Navigation Satellite System (GNSS) receiver based on a commercial purpose GNSS software receiver platform and verify its performance by performing experimental tests for various GNSS signals available in Korea region. The SX3, employed in this paper, is composed of an application program and a Radio Frequency (RF) frontend, and can capture and process multi-constellation and multi-frequency GNSS signals. All the signal processing procedure of SX3 is accessible by the receiver software designer. In particular for an easy research and development, the Application Programing Interface (API) of the SX3 has a flexible architecture to upgrade or change the existing software program, equipped with a real-time monitoring function to monitor all the API executions. Users can easily apply and experiment with the developed algorithms using a form of Dynamic Link Library (DLL) files. Thus, by utilizing this flexible architecture, the cost and effort to develop a GNSS receiver can be greatly reduced.

Design and Implementation of a GNSS Receiver Development Platform for Multi-band Signal Processing (다중대역 통합 신호처리 가능한 GNSS 수신기 개발 플랫폼 설계 및 구현)

  • Jinseok Kim;Sunyong Lee;Byeong Gyun Kim;Hung Seok Seo;Jongsun Ahn
    • Journal of Positioning, Navigation, and Timing
    • /
    • v.13 no.2
    • /
    • pp.149-158
    • /
    • 2024
  • Global Navigation Satellite System (GNSS) receivers are becoming increasingly sophisticated, equipped with advanced features and precise specifications, thus demanding efficient and high-performance hardware platforms. This paper presents the design and implementation of a Field-Programmable Gate Array (FPGA)-based GNSS receiver development platform for multi-band signal processing. This platform utilizes a FPGA to provide a flexible and re-configurable hardware environment, enabling real-time signal processing, position determination, and handling of large-scale data. Integrated signal processing of L/S bands enhances the performance and functionality of GNSS receivers. Key components such as the RF frontend, signal processing modules, and power management are designed to ensure optimal signal reception and processing, supporting multiple GNSS. The developed hardware platform enables real-time signal processing and position determination, supporting multiple GNSS systems, thereby contributing to the advancement of GNSS development and research.

Design of 4-Way Wilkinson Divider with Waveguide to Stripline Transition Used in The Monopulse Radar Front-end (도파관 천이 구조를 갖는 모노펄스 레이더용 4-Way 윌킨슨 분배기 설계)

  • Koh, Young-Mok;Ra, Keuk-Hwan
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.47 no.11
    • /
    • pp.69-76
    • /
    • 2010
  • From the present paper we researched about the design of 4-Way Wilkinson divider with waveguide to stripline transition which used to split the LO signal with equi-amplitude and equi-phase in the X-Band Monopulse radar RF front-end. The monopulse radar front end operating in the X-Band is composed of 3 waveguide reception mixers which down convert sum, azimuth and elevation signal to IF and one SSB waveguide mixers which generate X-Band test signal. It is required the 4-way divider with low loss, equi amplitude and equiphase splitting the LO signal to provide the LO signal to each mixer consisting RF frontend. In this paper we designed and fabricated the 4-Way Wilkinson divider with waveguide transition to divide the LO signal into equi-amplitude and equi-phase. The fabricated Wilkinson divider have the insertion loss 6.8dB, VSWR 1.06~1.28, and phase balance maximum 4.5degree for each output ports.