• 한국전자파학회논문지
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• 제23권11호
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• pp.1228-1238
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• 2012

본 논문에서는 RF 비아 구조를 이용하여 2가지 종류의 K-대역 CMOS FMCW 레이더 칩용 고주파 패키지를 설계, 제작 및 평가하였다. 패키지는 범용 PCB와 LTCC 공정을 이용하여 각각 제작되었다. 24 GHz를 기준으로 설계가 진행되었으며, 3차원 전자기 시뮬레이션을 통해 와이어 본딩과 RF 비아 구조의 임피던스 변화를 확인하였다. 비아 구조는 임피던스 부정합에 의한 손실을 억제하기 위해 $50{\Omega}$의 특성 임피던스를 가지도록 하였다. PCB 기반 패키지와 LTCC 패키지의 설계 검증을 위해 각 패키지의 RF 경로를 back-to-back 연결하여 시험용으로 제작하였고, 측정 결과 24 GHz에서 0.4 dB 이하의 우수한 삽입 손실을 얻었으며, 20~29 GHz 주파수 영역에서 0.5 dB 이하의 삽입 손실을 보였다. 반사 손실의 경우, 전체 주파수 영역에서 PCB 기반 패키지는 -13 dB 이하, LTCC 패키지는 -15 dB 이하의 특성이 측정되었고, back-to-back 연결의 리플 특성이 일반적으로 5 dB 정도의 반사 손실 열화를 초래하므로 패키지 자체의 RF 경로는 약 5 dB 정도 개선될 것으로 예측되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.329-332
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• 2002

In this paper a common design method fur RF receivers of different CDMA standards is introduced. The method adopted a new equation, receiver noise equation, for the analysis of each standard. The test conditions for RF receivers in four different CDMA standards, CDMA cellular, PCS, WCDMA, and cdma2000 are analyzed based on the receiver noise equation. With the result of the analysis, the specifications fer RF receivers of different CDMA standards are derived.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.411-414
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• 2004

This paper introduces a modulation method for digital wireless communication based on general DS-QPSK. The design and fabrication is for home networking application to a typical RF transmitter with DS-QPSK modulator. This modulator implemented using VHDL hardware programming language, the fabrication of IC chip $5{\times}5 mm^2$ was carried by 27th IDEC MPW(Multi Project Wafer) process in 0.35${\mu}m$ rule at Samsung Inc. This paper presented the important of this technology for the future application in wireless sensor. This module can be efficient usage for home network to transmit the RF wireless sensor system.

• ETRI Journal
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• 제33권1호
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• pp.6-12
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• 2011

A case study of an active transmitting patch antenna revealed a characteristic loop locus of DC power versus RF output power as drive frequency was varied, with an operational bandwidth substantially smaller than the impedance bandwidth of the radiator. An approximate simulation technique, based on separation of the output capacitance of the power transistor, yielded easily visualized plots of power dependence on internal load impedance, and a simple interpretation of the experimental results in terms of a near-resonance condition between the output capacitance and output packaging inductance.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.389-393
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• 2003

This paper describes the design of enhanced TSSI RF Power Detector which has wide dynamic range using switch and Log amp. This Power Detector consists of low and high gain loops, and they adaptively switched by output DC voltage which is proportioned to input power level. Because Power Detector needs to separate the channel, so architecture is heterodyne system having 70MHz intermediate frequency. This proposed RF Power Detector is settle to the satisfaction of Closed loop power control system for W-CDMA optic repeater, and the obtained dynamic range cover the higher than 50dB.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.410-413
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• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was DuPont #9599, which is applied for L TCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of l0[mA]

• 전기학회논문지
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• 제58권2호
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• pp.363-368
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• 2009

In the paper, we confirmed improvement Noise figure of the entire RF front-end using spiral inductor with PGS(Patterned Ground Shield) and current bleeding techniques. LNA design is to achieve simultaneous noise and input matching. Spiral inductor in input circuit of LNA inserted PGS for betterment of Q-factor. we modeling inductor using EM simulator, so compared with inductor of TSMC 0.18um. We designed and simulation the optimum structure of PGS using Taguchi's method. We confirmed enhancement of noise figure at LNA after substituted for inductor with PGS. Mixer designed using current bleeding techniques for reduced noise. We designed LNA using inductor with PGS and Mixer using current bleeding techniques, so confirmed improvement of noise figure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.410-413
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• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was Dupont ＃9599, which is applied for LTCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of 10[mA].

• 디지털콘텐츠학회 논문지
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• 제13권4호
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• pp.491-500
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• 2012

본 논문에서는 RF 송수신 시스템 칩 내부의 저잡음증폭기(LNA)와 전체 송수신기 시스템 테스트에 효과적인 새로운 루프백(Loopback) BIST 구조를 제안한다. 제안하는 테스트기법은 외부 테스트장비(Automatic Test Equipment)를 사용하는 기존의 테스트기법과 달리 테스트 모드에서 칩에 내장된 베이스밴드 프로세서를 테스터로 사용하므로써 테스트인가와 테스트평가등을 효율적으로 수행할 수 있는 장점을 갖는다. 높은 주파수의 테스트 출력신호는 낮은 주파수로 변환하여 베이스밴드 프로세서에서 평가하게 됨으로써 테스트용이도가 향상될 수 있다. 제안하는 테스트기법은 ATE와 같은 외부테스트장비의 필요를 최소화하고 테스트 시간과 비용을 줄여 결과적으로 칩 제조비용의 절감을 가능하게 해준다.

• International Journal of Aeronautical and Space Sciences
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• 제4권2호
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• pp.88-94
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• 2003

This paper describes the design of the Ka-band Antenna/RF system, which was developed for the experiment of the high-speed satellite communications with geostationary satellite. The design issues described here are the ka-band characteristics for having an optimum performance. and the system characteristic for having a reliable and an extensional operation.