• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.70-83
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• 2001

In this paper, the recent progress of RF MEMS research for wireless/mobile communications is reviewed. The RF MEMS components reviewed in this paper include RF MEMS switches, tunable capacitors, high Q inductors, and thin film bulk acoustic resonators (TFBARs) to become core components for constructing miniaturized on chip RF transceiver with multi-band and multi-mode operation. Specific applications are also discussed for each of these components with emphasis on for miniaturization, integration, and performance enhancement of existing and future wireless transceiver developments.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.187-190
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• 2000

We presents the construction of radio frequency pad area array package modules which operate at radio frequency of 224MHz, and proposes the structure of RF module packages to improve its electrical characteristics. The module of RF PAA package was constructed in the configuration of three dimensional stacked package and reduced size. RF PAA packages showed the optimized and improved gain of 2dB by partitioning the RF transceiver with 3 dimensional stacked PAA packages.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.2
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• pp.83-91
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• 2012

An RF energy detector for spectrum sensing in TV white space transceiver is presented. It is based on an RF active filtering technique that comprises a low-noise amplifier with a frequency-translation high-pass filtering feedfoward loop, which attenuates the unwanted sideband energy and only passes the wanted band energy. Unlike the conventional architecture, a new architecture that can attenuate both sidebands at the same time is proposed. A simplified system modeling method is presented to assess the non-ideality effects on the RF energy detector performances. System behavioral simulations demonstrate that the proposed architecture can be instrumental for realizaing a RF energy detector circuit in CMOS.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.9-18
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• 1998

A single RF transceiver chip for an extended GSM handset application was designedm, fabricated and evaluated. A RFIC was fabricated by using silicon BiCMOS process, and then packaged in 80 pin TQFP of $10 {\times} 10 mm^{2}$ in size. As a result, it was achieved guite reasonable integraty and good RF performance at the operation voltage of 3.3V. This paper describes development results of RF receiver section of the RFIC, which includes LNA, down conversion mixer, AGC, switched capacitor filter and down sampling mixer. The test results show that RF receiver section is well operated within frequency range of 925 ~960 MHz, which is defined on the extended GSM specification (E-GSM). The receiver section also reveals moderate power consumption of 67 mA and minimum detectable signal of -105 dBm.

• Journal of Digital Contents Society
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• v.13 no.4
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• pp.491-500
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• 2012

In this paper, a new loopback BIST structure which is effective to test RF transceiver chip and LNA(Low Noise Amplifier) in the chip is presented. Because the presented BIST structure uses a baseband processor in the chip as a tester while the system is under testing mode, the developed test technique has an advantage of performing test application and test evaluation in effectiveness. The presented BIST structure can change high frequency test output signals to a low frequency signals which can make the CUT(circuits under test) tested easily. By using this technique, the necessity of RF test equipment can be mostly reduced. The test time and test cost of RF circuits can be cut down by using proposed BIST structure, and finally the total chip manufacturing costs can be reduced.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.36-44
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• 2016

In this paper, an Impulse Radio-Ultra Wide band RF Transceiver for WBAN applications is implemented in $0.18{\mu}m$ CMOS technology. The designed RF transceiver support 3-5GHz UWB low band and employs OOK(On-Off Keying) modulation. The receiver employs non-coherent energy detection architecture to reduce complexity and power consumption. For the rejection of the undesired interferers and improvement of the receiver sensitivity, RF active notch filter is integrated. The VCO based transmitter employs the switch mechanism. As adapt the switch mechanism, power consumption and VCO leakage can be reduced. Also, the spectrum mask is always same at each center frequency. The measured sensitivity of the receiver is -84.1 dBm at 3.5 GHz with 1.579 Mbps. The power consumption of the transmitter and receiver are 0.3nJ/bit and 41 mW respectively.

• Journal of Biomedical Engineering Research
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• v.31 no.1
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• pp.20-26
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• 2010

The aim of this study was to test the feasibility of a wireless transceiver that can be inserted into the ear canal. The wireless technology could minimize the cosmetic problems of patients, and it can be applied to binaural hearing aids for improving speech perception. In order to implement the ear canal insertable transceiver, simple finite-difference time-domain (FDTD) simulations were carried out to determine the feasibility, and the hardware of the transceiver was implemented within the ear shell. The size of the implemented transceiver was only $7{\times}7mm$, and it could successfully transmit signals to external devices. In order to measure the radiation pattern, a simple RF phantom was used, and the maximum attenuation from the phantom was observed to be 23 dB when the reference antenna was placed at a distance of 2 m from the transmitter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.1
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• pp.148-154
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• 2005

This paper deals with performance degradations caused by RF I/Q impairments such as amplitude mismatch and phase mismatch in W-CDMA user equipment which uses QPSK(Quadrature Phase Shift Keying) modulation. The impacts of I/Q impairments on the BER(Bit Error Rate) are analyzed by using the variations of adjacent symbol distance. The BER versus amplitude mismatch and phase mismatch with QPSK constellation is reviewed through Matlab simulation. Performance degradation produced by RF I/Q impairments is measured with the implemented RF transceiver and modulation/demodulation test equipments through EVM(Error Vector Magnitude). The minimum performance requirements of amplitude mismatch and phase mismatch in W-CDMA user equipment are presented from the point of hardware implementation and the test method of the impairments is also included.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.342-345
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• 2014

An active frequency doubler monolithic microwave integrated circuit (MMIC) for E-band transceiver applications is presented in this letter. This MMIC has been fabricated in a commercial $0.1-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (pHEMT) process on a 2-mil thick substrate wafer. The fabricated MMIC chip has been measured to have a high output power performance of over 13 dBm with a high fundamental leakage suppression of more than 38 dBc in the frequency range of 71 to 86 GHz under an input signal condition of 10 dBm. A microstrip coupled line is used at the output circuit of the doubler section to implement impedance matching and simultaneously enhance the fundamental leakage suppression. The fabricated chip is has a size of $2.5mm{\times}1.2mm$.