• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.31-36
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• 2000

We developed embedded inductors in MCM-D substrate for RF applications. The increasing demand for high density packaging was the driving forces to the development of MCM-D technology. Most of these development efforts have been focused on high performance digital circuits. However, recently there is a great need fur mixed mode circuits with a combination of digital, analog and microwave devices. Mixed mode modules often have a large number of passive components that are connected to a small number of active devices. Integration of passive components into the high density MCM substrate becomes desirable to further reduce cost, size, and weight of electronic systems while improving their performance and reliability. The proposed MCM-D substrate was based on Cu/photosensitive BCB multilayer and Ti/Cu is used to form the interconnect layer. Seed metal was formed with 1000 $\AA$ Ti/3000 $\AA$ Cu by sputtering method and main metal was formed with 3 $\mu\textrm{m}$ Cu by electrical plating method. The multi-turn sprial inductors were designed in coplanar fashion. This paper describe the manufacturing process of integrated inductors in MCM-D substrate and the results of electrical performance test.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.964-970
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• 2013

This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 ${\mu}m$ consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 $mm^2$ and 0.029 $mm^2$, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.863-870
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• 2003

The digital transmission system entered in a RF region as digital system use IC chips of the speeder edge rate and clock speed nowadays. Optical path really was used in order to obtain the more capacity. In this paper, we described importance of electrical interconnect to get the signal integrity in optical module by simulation and experiment. 12 channel${\times}$2.5 G/ps optical parallel transmitter modules were manufactured by two different method ; access lines with microstrip and stripline type. We have clearly shown that the optical module adopting microstrip type with S$\sub$11/ $\geq$ -10 dB presents distortion but the optical module adopting stripline type with S$\sub$11/ $\leq$ : 15 dB obtains eye opening in 2.5 Gbis optical eye pattern response.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.9
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• pp.1098-1106
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• 2007

This paper presents active antenna diplexers implemented into an ultra-wideband CPW(Coplanar Waveguide) fed monopole antennas. The proposed active antenna diplexer is designed to direct interconnect the output port of a wideband antenna to the input port of two active(HEMT) devices, where the impedance matching conditions of the proposed active integrated antenna are optimized by adjusting CPW(Coplanar Waveguide) feed line to be the length of 1/20 $\lambda_0$(@5.8 GHz) in planar type wideband antenna. The measured bandwidth of the active integrated antenna shows the range from 2.0 GHz to 3.1 GHz and from 5.25 GHz to 5.9 GHz. The measured peak gains are 17.0 dB at 2.4 GHz and 15.0 dB at 5.5 GHz.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.11-11
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• 2000

이동통신기술의 급격한 발달로 고주파회로의 packaging과 interconnect 기술의 고성능화 와 저가격화에 대한 새로운 도전이 요구되고 있다‘ 대부분 기존의 무선통신 부품은 P PCB(Printed Wiring Board)기술을 활용하고 있으나 이러한 기술이 점차로 고주파화되는 경 향을 만족시킬수 없어 새로운 고주파 부품기술이 요구되고 있는 실정이다 .. RF 회로를 구성 하기 위하여 PCB소재의 환경적, 치수안정성 문제를 극복하기 위하여 L TCC(Low T Temperature Cofired Ceramics)기술이 최근 주목을 받고 있다. 차세대 이동통신 기술은 수십 GHz 이상의 고주파특성이 우수하고, 고성능의 초소형의 부품을 저가격으로 제조할수 있으며, 시장의 변화에 기민하게 대처할수 있는 기술이 요구되 고 있으며, 이러한 기술적 필요성에 부합할수 있도록 LTCC 기술이 제안되었다. 이러한 C Ceramic Interconnect 기술은 높은 신뢰성을 바탕으로 fine patterning 기술과 저가의 m metallizing 기술로 가능하게 되었다. 초고주파 통신부품기술은 미국과 유럽 등을 중심으로 G GHz 대역또는 mm wave 대역의 기술에 대하여 치열한 기술개발 경쟁을 벌이고 있으며, 이 러한 고주파 패키징 기술을 바탕으로 미래의 군사, 항공, 우주 및 이동통신 기술에 지대한 영향을 미칠수 있는 기반기술로 자리잡을 전망이다. L LTCC 기술은 기존의 후막혼성기술에 비하여 공정이 단순하고 대량생산이 가능하고 가 격이 비교적 저렴하다. 또한 다층구조로 제작할수 있고, 수동소자를 내장할수 있어 회로의 소형화와 고밀도화가 가능하다. 특히 무선으로 초고속 정보를 처리하기 위하여 이동통신기 기의 고주파화가 빠르게 진행됨에 따라서 고분자재료에 비하여 고주파특성이 우수할뿐아니 라 환경적, 치수안정성이 우수한 세라믹소재플 사용함으로써 고주파 손실율을 저감할 수 있 다 .. LTCC 기술은 후막회로 기술과 tape dielectric 기술이 결합된 기술이다. 표준화된 소재 와 공정기술을 활용하여 저가격으로 고성능소자플 제작할 수 있으며, 전극재료로서 높은 전 도도를 갖고 있는 Ag, Cu, Au 및 Pd! Ag릎 사용함으로써 고주파 손실을 저감시킬 수 있다. L LTCC 기술이 최종적으로 소형화, 고기능 고주파 부품기술로 지속적으로 발전하기 위하여 무수축(Zero shrinkage) 소성기술, 광식각 후막기술 등이 원천기술로서 확립될 수 있어야 하 며, 특히 국내의 이동통신 기술에 대한 막대한 투자에도 불구하고 차세대 이동통신 부품기 술에 대한 개발은 상대적으로 미흡한 실정이므로 국내에 LTCC 관련 소재공정 및 부품소자 기술에 대한 개발투자가 시급히 이루워져야 할 것으로 판단된다. 본 발표에서는 지금까지 국내외 LTCC 기술의 발전과정을 정리하였고, 현재 이 기술의 응용과 소재와 공정을 중심으로한 개발현황에 대하여 조사하였으며, 앞으로 LTCC가 발전 해야할 방향을 제시하고자 한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.5
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• pp.445-453
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• 2016

This paper presents the implementation and design of the 1T-1R wireless HD video streaming systems over 28 GHz mmWave frequency using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system uses USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transceived from USRP RIO up or down converts to 28 GHz by using self-designed 28 GHz RF transceiver modules and it is finally communicated HD video data through self-designed $4{\times}8$ sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express ${\times}4$ to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 25.85 dBc and to transceive HD video in experiment environment anywhere.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.8
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• pp.42-50
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• 2007

This paper presents design methods for dual-frequency(2.4/5.8GHz) active receiving antennas. The proposed active receiving antennas are designed to interconnect the output port of a wideband antenna to the input port of an active device of High Electron Mobility Transistor directly and to receive RF signals of 2.4GHz and 5.2GHz simultaneously where the impedance matching conditions are optimized by adjusting the length of $1/20{\lambda}_0$(@5.8GHz) CPW transmission line in the planar antenna The bandwidth of implemented dual-frequency active receiving antennas is measured in the range of 2.0GHz to 3.1GHz and 5.25GHz to 5.9GHz. Gains are measured of 17.0dB at 2.4GHz and 15.0dB at 5.2GHz. The measured noise figure is 1.5dB at operating frequencies.