1 |
K. Ikeuchi, M. Takamiya, and T. Sakurai, "Through silicon capacitive coupling(TSCC) interface for 3D stacked dies", IEEE 3D Systems Integration Conference, pp. 1-5, 2012.
|
2 |
M. Scandiuzzo, R. Cardu, S. Cani, S. Spolzino, L. Perugini, E. Franchi, R. Canegallo, and R. Guerrieri, "3 D system on chip memory interface based on modeled capacitive coupling interconnections", IEEE 3 D Systems Integration Conference, pp. 1-4, 2010.
|
3 |
Gu Qun, Z. Xu, Jenwei Ko, and, M. -C. F. Chang, "Two 10 Gb/s/pin low-power interconnect methods for 3D ICs", IEEE International Solid State Circuits Conference(ISSCC), pp. 448-614, 2007.
|
4 |
H. Ishikuro, N. Miura, and T. Kuroda, "Wideband inductive-coupling interface for high-performance portable system", IEEE Custom Integrated Circuits Conference(CICC), pp. 13-20, 2007.
|
5 |
M. Saen, K. Osada, and Kuroda, "3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link", IEEE J. Solid-State Circuits, vol. 45, no. 4, pp 856-862, Apr. 2010.
DOI
ScienceOn
|
6 |
W. R. Davis, J. Wilson, S. Mick, and J. Xu, "Demystifing 3D ICs: The pros and cons of vertical", IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov.-Dec. 2005.
DOI
ScienceOn
|
7 |
김소영, "3D IC에서의 인터페이스 기술", 대한전자공학회지, 36(9), pp. 1001-1009, 2009년 9월.
|
8 |
N. Miura, T. Kuroda, "Inductive - coupling transceiver for 3D system integration", IEEE Integrated Circuit Design and Technology(ICICDT), pp. 1-4, 2007.
|