• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.96-99
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• 2008

This paper describes a $0.13-{\mu}m$ CMOS RF switch for $3{\sim}5$ GHz UWB band(mode 1). It can improve isolation characteristics between ports by using deep n-well RF devices while their source and body terminals are separated. From the measurement results, the proposed T/R switch is comparative to the on-wafer probing measurement results of the series-shunt T/R switches. When the proposed T/R switch operates as Tx mode, measured insertion loss from Tx to output port is less than 1.5 dB and isolation between Tx and Rx is more than 27 dB for $3{\sim}5$ GHz. Return loss for the Tx port is more than -10 dB and input P1dB is +10 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.675-681
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• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• IEIE Transactions on Smart Processing and Computing
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• 제5권3호
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• pp.164-168
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• 2016

A low insertion-loss, high-isolation switch based on single pole double throw (SPDT) for a 2.4GHz Bluetooth low-energy transceiver is presented in this paper. In order to increase isolation, the body floating technique is implemented. Based on characteristics whereby the ratio of the sizes of the shunt and the series transistors significantly affect the performance of the switches, the device sizes are optimized. A simple matching network is also designed to enhance the insertion loss. Thus, the SPDT switch has high isolation and low insertion loss without increasing the complexity of the circuit. The proposed SPDT is designed and simulated in a complementary metal-oxide semiconductor 65nm process. The switch has a $530{\mu}m{\times}270{\mu}m$ area and achieves 0.9dB, 1.78dB insertion loss and 40dB, 41dB isolation of transmission, reception modes, respectively.

• International journal of advanced smart convergence
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• 제11권4호
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.