• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.1-9
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• 1999

This paper presents an analytic 3rd order calculation methods, without simulations, for delay time of RC-class circuits which are conveniently used to on-chip interconnects. While the proposed method requires comparable evaluation time than the previous 2nd order calculation method, it ensures more accurate results than those of 2nd order method. The proposed analytic delay calculation method guarantees allowable error tolerances when compared to the results obtained from the AWE (Asymptotic Waveform Evaluation) technique and has better performance in evaluation time as well as numerical stability. The first algorithm of the proposed method requires 8 moments for the 3rd order approximation and yields more accurate delay time approximation. The second algorithm requires 6 moments for the 3rd order approximation and results in shorter evaluation time, the accuracy of which may be less than the first algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.1032-1040
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• 2010

This paper describes implementation of electonic seal (E-Seal) of a container based on ISO 18185 standard and development of monitoring systems checking E-Seal device and cargo states in the container for secure transportation from departure to destination. For lack of definition on confidentiality support in ISO 18185-4 standard, it is vulnerable to security attack such as sniffing. To cope with this, we developed encryption/decryption functions implementing RC5 and AES-128 standards and compared their performance. Experimental results showed that RC5 outperformed AES-128 in terms of time delay. In addition, RC5 had an advantage under the condition of large sized messages as well as CPUs with low performance. However, the portion of encryption/decryption processing time was less than 1 percent of response time including communication delay between E-Seal tags and readers. Hence, the performance difference between RC5 and AES-128 standards was trivial, which revealed that both specifications were allowable in developed systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.484-492
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• 2015

This paper proposes a PWM phase-shift circuit to make that the LED lighting system distributes the channel currents evenly for any number of LED strings by generating evenly phase-shifted PWM signals for multiple LED driver ICs. The evenly distributed channel currents reduce the peak current, the decoupling capacitor size, and EMI noise. The PWM phase-shift circuit makes an arbitrary degree of PWM phase-shift by using a resistor and a capacitor. It measures the RC delay once. It reduces the number of external resistors and capacitors by providing zero and 180 degree phase-shift modes requiring no resistor and capacitor. An LED driver IC with the PWM phase-shift circuit was fabricated with a $0.35{\mu}m$ BCDMOS process. The PWM phase-shift circuit receives a PWM signal of 50 Hz~20 kHz at $f_{CLK}=450kHz$ and it generates a $0{\sim}360^{\circ}$ phase-shifted PWM signal with $R=0{\sim}1.1M{\Omega}$ at C=1 nF and $f_{PWM}=1kHz$. The measured phase errors are 1.74~3.94% due to parasitic capacitances.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 1998.11a
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• pp.162-165
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• 1998

A certain degree of energy saving can be possible by controlling the delay time of occupancy sensor. In this paper a control circuit is designed for automatic control of delay time setting appropriate to different situations using a digital counter, two latches and an adder. The delay time is controlled by adjusting the time constant of RC circuit through on-off control of switching devices according to adder output, which determines the base current level of switching devices. And from PSpice simulation it is verified to function properly.

• Journal of Power Electronics
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• v.13 no.3
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• pp.409-418
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• 2013

This paper presents an enhanced control strategy which consists of a proportional-integral controller and a repetitive controller (RC) for improving the voltage performance of distributed generation (DG) under nonlinear load conditions. The proposed voltage controller is able to maintain a sinusoidal voltage at the point of common coupling (PCC) of the DG regardless of the harmonic voltage drop in the system impedance due to nonlinear load currents. In addition, by employing the delay time of the RC at one-sixth of the fundamental period, the proposed RC can overcome the slow response drawback of the traditional PI-RC. The proposed control strategy is analyzed and the design of the RC is presented in detail. The feasibility of the proposed control strategy is verified through simulation and experimental results.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of Power Electronics
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• v.17 no.1
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• pp.172-180
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• 2017

The repetitive control (RC) strategy is widely used in AC power systems because of its high performance in tracking period signal and suppressing steady-state error. However, the dynamic response of RC is determined by the fundamental period delay $T_0$ existing in the internal model. In the current study, a ($nk{\pm}i$)-order harmonic RC structure is proposed to improve dynamic performance. The proposed structure has less data memory and can improve the tracking speed by n/2 times. $T_0$ proves the effectiveness of the ($nk{\pm}i$)-order RC strategy. The simulation and experiments of ($6k{\pm}1$)-order and ($4k{\pm}1$)-order RC strategy used in the voltage source inverter is conducted in this study to control the harmonic current source, which shows the validity and advantages of the proposed structure.

• Journal of the Korea institute for structural maintenance and inspection
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• v.2 no.2
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• pp.202-208
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• 1998

To investigae the effect of anchorage type of carbon fiber sheet (CFS) on flexural behavior of RC beams, the loading test of RC beams reinforced with CFS was conducted in variable of anchorage Type such as bolting anchorage and U type anchorage using CFS. This study can be summarized as follows ; It is confirmed experimentally that the bolting anchorage and U type anchorage with CFS is very effective to delay the bond failure and prevent the peeling of CFS. Also, the anchorage type applied with this study is very effective to improve the ductility compared with the improving of maximum flexural strength of RC beams. It is believed that the anchorage type used this study must secure the ductile capacity of above 3 for the flexural strengthening of RC beams. In the future, it is required to obtain the data about anchorage type of CFS for utilization of field work as well as investigate the ductile capacity of conventional study of anchorage type

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.6
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• pp.354-360
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• 2002

Delay estimation must be simple and efficient, since millions or more delay calculations may be required during a timing-driven placement stage. We have developed a new Modified Elmore delay estimation method, which is significantly more accurate than the original Elmore delay by considering resistance shielding effects, but has the same order of complexity with that of Elmore delay. Experimental results show that the suggested technique can significantly reduce the error in estimated delay, from 31.6 ~ 145.2% to 2.5 ~ 22.7%.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.9-12
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• 2008

For the large-sized and post-ultra definition TFT-LCD, improved drivability is prerequisite not only for the integration of driving circuit on glass but also for the chargeability of each pixel. In order to meet required drivability, currently adopted process architecture and materials are modified for the RC delay reduction, including the drastic increase of gate bus thickness and its related solution for step coverage. We present new process architecture and material selection for the next generation TFT-LCD devices.