• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• Journal of IKEEE
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• v.23 no.2
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• pp.571-579
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• 2019

Visible light communication (VLC) performs illumination and communication simultaneously, thus it is important to prevent the flicker due to the optical power variation during data transmission and at the same time to have dimming control capability. In this paper, we used Manchester code for flicker-prevention and dimming control. In the transmitter, the duty factor of the Manchester code was used for controlling the LED illumination. In the receiver, the edge-spike signals of an RC-high pass filter were used for recovering the Manchester code while preventing the adjacent noise light. In experiments, the LED light was kept flicker-free and the average optical power was controlled in the range of 8~68 % of the continuous wave (CW) LED light by changing the duty factor of the Manchester code.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.283-289
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• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.93-96
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• 2000

This paper has been proposed an audio DAC structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter on-a-chip. The passband ripple(< 0.41${\times}$fs), passband attenuation(at 0.41${\times}$fs) and stopband attenuation(> 0.59${\times}$fs) of the Δ$\Sigma$ modulator output using the proposed digital interpolation filter had ${\pm}$ 0.001 ［㏈］, -0.0025［㏈］ and -75［㏈］, respectively. Also the inband group delay was 30.07/fs［s］ and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20［㏈］ approximately at 65［㎑］, out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.12
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• pp.1120-1125
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• 2000

This paper presents a technique for estimating the attitude of a model helicopter at near hovering using a combination of inertial and non-inertial sensors such as gyroscope and potentiometer. To estimate the attitude of helicopter a simplified indirect Kalman filter based on sensor modeling is derived and the characteristics of sensors are studied, which are used in determining the optimal Kalman gain. To verify the effectiveness of the proposed algorithm simulation results are presented with real flight data. Our approach avoids a complex dynamic modeling of helicopter and allows for an elegant combination of various sensor data with different measurement frequencies. We also describe the method of implementation of the algorithm in the model helicopter.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1572-1580
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• 1995

In this paper, a modified Chebyshev low-pass filter function is proposed. The modified Chebyshev filter function exhibits ripples diminishing toward .omega. = 0 in the passband. So, the modified filter function is realizable in the passive doubly-terminated ladder network for the order n even or odd, thus lending itself amenable to active RC or switched capacitor filters through the simulation techniques. Besides the passive doubly-terminated ladder realizability, lower pole-Q values of the modified function are accountable for improved phase and delay characteristics, as compared to classical function. We have designed the 6th order passive doubly-terminated network using the modified function. And then a continuous-time DDA(Differential Difference Amplifier) filter, which has no matching requirement, is realized by leap-frog simulation technique for fabrication. In the HSPICE simulation results, we confirmed that the designed continuous-time DDA filter characteristics are agreement with the passive filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1579-1589
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• 1997

This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.7-16
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• 2015

The transmitter of quadrature multiplexed GMSK (QM-GMSK) is composed of two quadrature multiplexed GMSK modulators. QM-GMSK has a slightly increased spectrum main lobe compared with $Q^2PSK$ or QMSK, but it has highly suppressed side lobes. As a result, practical spectrum efficiency of QM-GMSK is achieved. By replacing the baseband elementary pulses of QM-GMSK with their approximate, the squared sinusoid of half-period, offset-$Q^2PSK$($OQ^2PSK$) is obtained. The $OQ^2PSK$ signal has similar spectral properties to QM-GMSK. The transmitter of $OQ^2PSK$ can be simply implemented without the Gaussian lowpass filter, which is required in QM-GMSK transmitter. In this paper, we propose an overlapped pulse shaping in $OQ^2PSK$ with RC(raised-cosine) or SRC(squared raised-cosine) pulses of length longer than the symbol period. Power spectrum of the proposed modulation scheme exhibits further suppressed side lobes, hence enhanced spectrum efficiency is obtained. Simulation results indicate that BER performance of the proposed scheme is comparable to that of $OQ^2PSK$.