• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.445-448
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• 2005

A new high efficiency phase shifted full bridge (PSFB) converter for sustaining power module of plasma display panel (PDP) is proposed in this paper .The proposed converter employs the rectifier of voltage doubler type without output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the level of the output voltage. Therefore, no dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed and a high efficiency as well as low noise cutout voltage can be realized. In addition, due to elimination of the large output inductor, it features a simple structure, lower cost, less mass, and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS ) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell makes the current stresses of the primary switches and rectifier diodes reduced. In this paper, the operational principles, analysis of the proposed converter, and the experimental results are presented.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.74-74
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• 2000

낮은 유전상수(k$\leq$3)와 높은 열적안정성(>4$25^{\circ}C$)은 초고집적회로(ULSI)기술에서 RC 지연을 해결하기 위한 금속배선의 중간 절연층으로서의 2개의 가장 중요한 특성이다. 본 연구에서는 cyclohezane을 precursor로 사용하여 plasma enhanced chemical vapor deposition(PECVD)방법으로 유기박막을 성장시켰으며 낮은 유전상수와 높은 열적안정성을 동시에 확보하기 위하여 열적안정성은 좋지 않지만 유전상수가 낮은 박막(soft layer)위에 유전상수는 다소 높지만 열적안정성이 좋은 박막(hard layer)을 얇게 증착하여 hard layer/soft layer의 2층 구조를 형성하여서 구조적, 전기적 특성을 조사하였다. 유기박막은 5$0^{\circ}C$로 유지된 reactor 내부에서 argon(Ar) plasma에 의해 증착되었으며 platinum(Pt)기판과 silicon 기판위에 동시에 증착하였다. Pt 기판위에 증착한 시편으로 유전상수, I-V 등 전기적 특성을 측정하였고, silicon 기판위에 증착한 시편으로 열적안정성과 구조적 특성등을 분석하였다. 증착압력 0.2Torr에서 plasma power를 5W에서90W로 증가할 때 유전상수는 2.36에서 3.39로 증가하였으며 열적안정성은 90W에서 180W로 증가하였을 때 유전상수는 2.42에서 2.79로 증가하엿고 열적안정성은 모두30$0^{\circ}C$이하였다. 단일층 구조에서는 유전상수가 낮은 박막은 열적으로 불안정하고 열적 안정성이 좋은 박막은 유전상수가 다소 높은 문제가 나타났다. 이런 문제를 해결하기 위하여 2 Torr, 120W에서 증착한 유전상수가 2.55이고 열적으로 불안정한 박막을 soft layer로 5150 증착하고 그 위에 0.2Torr, 90W에서 증착한 유전상수가 3.39이고 열적으로 45$0^{\circ}C$까지 안정한 박막을 hard layer로 360 , 720 , 1440 증착하였다. 증착된 2층구조 박막의 유전상수는 각각 2.62, 2.68, 2.79이었으며 열적안정성 측정에서는 40$0^{\circ}C$까지 두께 감소가 보이지 않았다. 그러나 SEM 측정에서 열처리 후 표면이 거칠어지는 현상이 발견되었다.

• Journal of the Korea institute for structural maintenance and inspection
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• v.27 no.5
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• pp.67-74
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• 2023

A large number of concrete structures are built and used around the world. To ensure their safe and continuous use, these structures require constant inspection and maintenance. While man-powered inspection and maintenance techniques are efficient, they can only provide intermittent status checks at the time of on-site inspection. Therefore, there is a growing need for a system that can continuously monitor the condition of the structure. A study was conducted to detect cracks and damage by installing a conductive coating on the surface of a concrete structure. A parallel resistance pattern that can monitor the occurrence and progression of cracks was developed by reflecting the structural characteristics of concrete structure. An empirical study was conducted to veryfy the application of the proposed method. The crack detection pattern was installed on the reinforced concrete beams, and the crack monitoring method was verified through applying a load on the beams.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.368-373
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• 1998

As device dimensions approach submicrometer size in ULSI, the demand for interlayer dielectric materials with very low dielectric constant is increased to solve problems of RC delay caused by increase in parasitic resistance and capacitance in multilevel interconnectins. Fluorinated amorphous carbon in one of the promising materials in ULSI for the interlayer dielectric films with low dielectric constant. However, poor thermal stability and adhesion with Si substrates have inhibited its use. Recently, amorphous hydrogenated carbon (a-C:H) film as a buffer layer between the Si substrate and a-C:F has been introduced because it improves the adhesion with Si substrate. In this study, therfore, a-C:F/a-C:H films were deposited on p-type Si(100) by ECRCVD from $C_2F_6, CH_4$and $H_2$gas source and investigated the effect of forward power and composition on the thickness, chemical bonding state, dielectric constant, surface morphology and roughness of a-C:F films as an interlayer dielectric for ULSI. SEM, FT-IR, XPS, C-V meter and AFM were used for determination of each properties. The dielectric constant in the a-C:F/a-C:H films were found to decrease with increasing fluorine content. However, the dielectric constant increased after furnace annealing in $N_2$atomosphere at $400^{\circ}C$ for 1hour due to decreasing of flurorine content. However, the dielectric constant increased after furnace annealing in $N_2$atmosphere at $400^{\circ}C$ for 1hour due to decreasing of fluorine concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• The Korean Journal of Nuclear Medicine
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• v.33 no.1
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• pp.100-109
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• 1999

Purpose: Preamplifier and amplifier are very important parts for developing a portable counting or imaging gamma probe. They can be used for analyzing pulses containing energy and position information for the emitted radiations. The commercial Nuclear Instrument Modules (NIMs) can be used for processing these pulses. However, it may be improper to use NIMs in developing a portable gamma probe, because of its size and high price. The purpose of this study was to develop both preamplifier and amplifier and measure their performance characteristics. Materials and Methods: The preamplifier and amplifier were designed as a charge sensitive device and a capacitor resistor-resistor capacitor (CR-RC) electronic circuit, respectively, and they were mounted on a print circuit board (PCB). We acquired and analyzed energy spectra for Tc-99m and Cs-137 using both PCB and NIMs. Multichannel analyzer (Accuspec/A, Canberra Industries Inc., Meriden Connecticut, U.S.A) and scintillation detectors (EP-047(Bicron Saint-Gobain/Norton Industrial EP-047 (Ceramics Co., Ohio, U.S.A) with $2"{\times}2"$ NaI(T1) crystal and R1535 (Hamamatsu Photonics K.K., Electron Tube Center, Shizuoka-ken, Japan) with $1"{\times}1"$ NaI(T1) crystal were used for acquiring the energy spectra. Results: Using PCB, energy resolutions of EP-047 detectors for Tc-99m and Cs-137 were 12.92% and 5.01%, respectively, whereas R1535 showed 13.75% and 5.19% of energy resolution. Using the NIM devices, energy resolutions of EP-047 detector for Tc-99m and Cs-137 were measured as 14.6% and 7.58%, respectively. However, reliable energy spectrum of R1535 detector could not be acquired, since its photomultiplier tube (PMT) requires a specific type of preamplifier. Conclusion: We developed a special preamplifier and amplifier suitable for a small sized gamma probe that showed good energy resolutions independent of PMT types. The results indicate that the PCB can be used in developing both counting and imaging gamma probe.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.