• 한국태양에너지학회 논문집
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• 제31권6호
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• pp.49-56
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• 2011

In this study a novel cogeneration system driven by low-temperature sources at a temperature level below $190^{\circ}C$ is investigated by first and second laws of thermodynamics. The system consists of Organic Rankine Cycle(ORC) and an additional heat generation as a parallel circuit. Seven working fluids of R143a, R22, R134a, R152a, $iC_4H_{10}$(isobutane), $C_4H_{10}$(butane), and R123a are considered in this work. Maximum mass flow rate of a working fluid relative to that of the source fluid and optimum turbine inlet pressure are considered to extract maximum power from the source. Results show that due to a combined heat and power generation, both the efficiencies by first and second laws can be significantly increased in comparison to a power generation, however, the second law efficiency is more resonable in the investigation of cogeneration systems. Results also show that the working fluid for the maximum system efficiency depends on the source temperature.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.159-162
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• 2002

A software, called touch-one, is developed about the determination of short-circuit values and protective co-ordination in power system. The used solution algorithm reviewed intensively, and the protective co-ordination determination technique presented by using the circuit-breaker's current-limitation characteristic. The protective coordination concerns the behaviour of two devices placed in series in an electrical network, with a short-circuit downstream circuit-breaker. It has two basic principles: First, discrimination which is an increasing requirement of low voltage electrical distribution systems. Second, which is less well known: cascading, which consists of installing a device, whose breaking capacity is less than the three-phase short-circuit current at its terminals and helped by main circuit-breaker. With this software, we can construct a electric-power system which is reliable and economic according to user's purpose.

• 전자공학회논문지C
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• 제35C권4호
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• ETRI Journal
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• 제26권6호
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• pp.669-672
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• 2004

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters $C_g=C_T=C_{clk}=1\;aF,\;R_T=5\;M{\Omega},\;V_{clk}=40\;mV$, and $V_{in}=20\;mV$. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.705-706
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• 2006

Generally Short Circuit Test of transformers are tested according to IEEE std C57.12.00-2000, IEC 60076-5(2000-07), ES148(1998.6.26) or KS C4309(2003). But ES148(1998.6.26) is same as IEEE std C57. 12.00-2000 and KS C4309(2003) is revising coincidence with IEC 60076-5(2000-07). On this study condition of the transformers before short circuit test, calculation method for test current peak value, tolerance on the asymmetrical peak and r.m.s value, short circuit testing procedure, number of short circuit test, duration short circuit test, and detection of faults and evaluation of short circuit test result will be compared with ANSI and IEC.

• 대한전자공학회논문지
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• 제23권6호
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• pp.923-928
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• 1986

This paper describes the design and fabrication of a high performance digital tuning analog component integrated circuit that contains a television station detector and decoders(H and L types). When the comparator level sampling method is used, this integrated circuit can be used as a stable channel selector for an external circuit with very large signal variation. It has been fabricated using the SST bipolar standard process and its chip size is 2.2x2.1mm\ulcorner As a result, we have succeeded in fabricating the IC that satisfies the D.C characteristics, and the channel station detector and decoder function.

• 전자공학회논문지C
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• 제34C권8호
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• Journal of Power Electronics
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• 제9권2호
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• pp.232-242
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• 2009

In this paper, a matrix converter with improved low frequency output performance is proposed by achieving a one-step commutation owing to a general commutation circuit applicable to n-phase to m-phase matrix converters. The commutation circuit consists of simple resister and capacitor components, leading to a very stable, reliable and robust operation. Also, it requires no extra sensing information to achieve commutation, allowing for a one-step commutation like a conventional dead time commutation. With the dead time commutation strategy applied, the distortion caused by commutation delay is analyzed and compensated, therefore leading to better output linear behavior. In this paper, detailed commutation procedures of the R-C commutation circuit are analyzed. A selection of specific semiconductor switches and commutation circuit components is also provided. Finally, the effectiveness of the proposed commutation method is verified through a two-phase to single-phase matrix converter and the feasibility of the compensation approach is shown by an open loop space vector modulated three-phase matrix converter with a passive load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.600-602
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• 2006

Some abnormal signals diagnostics and analysis through an important equivalent circuits modeling for passive elements under severe accident conditions have been performed. Unlike the design basis accidents, there are inherently some uncertainties in the instrumentation capabilities under the accident conditions. So, the circuit simulation analysis and diagnosis methods are used to assess instruments in detail when they give apparently abnormal readings as an accident alternative method. The simulations can be useful to investigate what the signal and circuit characteristics would be when similar to a variety of symptoms that can result from the environmental conditions such as high temperature, humidity, and pressure condition. In this paper, a new simulator through an analysis of the important equivalent circuits modeling under temperature accident conditions has been designed, the designed simulator is composed of the LabVIEW code as a main tool and the out-put file of the Multi-SIM code as an engine tool is exported to in-put file of the LabVIEW code. The procedure for the simulator design was divided into two design steps, of which the first step was the diagnosis method, the second step was the circuit simulator for the signal processing tool. It has three main functions which are a signal processing tool, an accident management tool, and an additional guide from the initial screen. This simulator should be possible that it could be applied a output signal analysis to some transient signal by variation of the resistance passive elements in the R-L-C equivalent circuit modeling under various degraded conditions in NPPs.

• 대한전자공학회논문지SD
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• 제39권1호
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• pp.67-75
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• 2002

본 논문에서는 대략적인 PEEC 방법에 대해 논의 하고, 도선에 대하여 PEEC 등가회로를 구성하였으며, 주어진 등가회로로 부터 시스템의 행렬을 구하고, 이 행렬을 수치 해석적인 방법을 이용한 시뮬레이션을 수행하여 노드에서의 전압과 전류를 구하였다. PEEC 등가 회로를 구성하기 위해서, PEEC 등가 회로를 구성하는 성분(R, L, C)을 유한 요소법(finite element method)을 이용한 시뮬레이터를 이용하여 추출하였으며, 생성된 등가 회로에 대한 과도 해석을 수행하였다.