• Journal of Power Electronics
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• v.11 no.3
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• pp.375-380
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• 2011

A STATic synchronous COMpensator (STATCOM) is a shunt connected voltage source converter (VSC) based FACTS controller using Gate Turn Off (GTO) power semiconductor devices employed for reactive power control. The operation principal is similar to that of a synchronous condenser. A typical application of a STATCOM is voltage regulation at the midpoint of a long transmission line for the enhancement of power transfer capability and/or reactive power control at the load centre. This paper presents the modeling of STATCOM with twenty four pulse three level VSC and Type-1 controller to regulate the reactive current or the bus voltage. The performance is evaluated by transient simulation. It is observed that, the STATCOM shows excellent transient response to step change in the reactive current reference. While the eigenvalue analysis is based on D-Q model, the transient simulation is based on both D-Q and 3 phase models of STATCOM (which considers switching action of VSC).

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2952-2965
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• 2023

Advanced reactors, such as Small Modular Reactors or existing Nuclear Power Plants, often use Field Programmable Gate Array (FPGA) based controllers in new Instrumentation and Control (I&C) system architectures or as an alternative to existing analog-based I&C systems. Compared to CPU-based Programmable Logic Controllers (PLCs), FPGAs offer better overall performance. However, programming functions on FPGAs can be challenging due to the requirement for a hardware description language that does not explicitly support the operation of real numbers. This study aims to implement the Reactor Trip (RT) functions of the existing analog-based Reactor Protection System (RPS) using FPGAs. The RT equations for Overtemperature delta Temperature and Overpower delta Temperature involve dynamic compensators expressed with the Laplace transform variable, 's', which is not directly supported by FPGAs. To address this issue, the trip equations with the Laplace variable in the continuous-time domain are transformed to the discrete-time domain using the Z-transform. Additionally, a new operation based on a relative value for the equation range is introduced for the handling of real numbers in the RT functions. The proposed approach can be utilized for upgrading the existing analog-based RPS as well as digitalizing control systems in advanced reactor systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.18 no.1
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• pp.43-52
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• 2006

Numerical model tests are done in order to evaluate impact zone of low salinity water on outer region of the developing Saemankeum reservoir. Also saline mixing processes are investigated f3r the inner reservoir with consideration of Mankyoung and Donjin riverine flood discharges when sea water is passing freely through gate. In these analyses 2-d ADCIRC, 3-d TIDED3D and CE-QUAL-ICM models are used. Through models tests, it is found that inner reservoir mixing process caused by inflow of outer sea water occurs gradually. It takes at least one month for complete mixing on Mankyoung part and 6 month on Dongjin part of the reservoir. When Sinsi or Garyeok gates are opened to control inner reservoir level, discharging velocities decrease exponentially from the gates, but show very strong currents of 0.5m/sec to the 10Km region apart. These results imply that hydrodynamic circulation and ecosystem of frontal region of the Saemankeum dike might be affected in amount by gate operations, since low saline inner waters are discharged periodically at ebb tide according to tidal level.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.3
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• pp.277-282
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• 2005

This paper describes a step-down AC voltage regulator using an AC chopper and auxiliary transformer, which is a series connected to the main input. The detail design of the AC regulator, logic and PWM pattern of the AC chopper is described and the three-phase AC regulator using two single­phase AC choppers with a three transformer configuration is proposed for three-phase application. The proposed three-phase system has the advantages of lower system cost due to reduced switch number and gate driver circuit as well as advantages of decreased size and weight because it uses a series compensated scheme. The proposed AC regulator has many benefits such as fast voltage control, high efficiency and simple control logic. Experimental results indicate that it can be used as a step-down AC voltage regulator for power saving purposes very efficiently.

• Journal of Dental Anesthesia and Pain Medicine
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• v.23 no.6
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• pp.317-325
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• 2023

Background: Local anesthetic injections may induce pain in children, leading to fear and anxiety during subsequent visits. Among the various approaches recommended to reduce pain, one is the use of a Buzzy Bee^TM device that operates on the concept of gate control theory and distraction. The literature regarding its effectiveness during the deposition of local anesthesia remains limited; hence, the aim of the present study was to determine the efficacy of extraoral cold and vibrating devices in reducing pain perception during the deposition of local anesthesia. Methods: A split-mouth crossover study in which 40 children aged 3-12 years requiring maxillary infiltration or inferior alveolar nerve block for extractions or pulp therapy in the maxillary or mandibular posterior teeth were included. The control intervention involved the application of topical anesthetic gel for one minute (5% lignocaine gel), followed by the administration of local anesthetic (2% lignocaine with 1:80,000 adrenaline) at a rate of 1 ml/ minute. Along with the control protocol, the test intervention involved using the Buzzy Bee^TM device for 2 minutes before and during the deposition of the local anesthetic injection. The heart rate and face, legs, arms, cry, and consolability revised (FLACC-R) scale scores were recorded by the dentist to assess the child's pain perception. Results: The mean age of the participants in Group A and Group B was 7.050 ± 3.12 years and 7.9 ± 2.65 years respectively. A reduction in the mean heart rate and FLACC-R score was observed during the deposition of local anesthetic solution in the tissues when the Buzzy Bee^TM was used in both groups at different visits in the same subjects (P < 0.05) The Buzzy Bee^TM device was effective in reducing the heart rate and FLACC-R scores when used during maxillary infiltration and inferior alveolar nerve block local anesthesia techniques (P < 0.05). Conclusion: The use of extraoral cold and vibrating devices significantly reduces pain perception during local anesthetic deposition in pediatric patients. Considering the results of this study, the device may be incorporated as an adjunct in routine dental practice while administering local anesthesia in children.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.201-208
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• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.43-49
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• 2021

A small infrared image homing system is a tracking system that has an infrared image sensor that identifies a target through the day and night infrared image processing of the target on the ground and searches for and detects the target with respect to the main target. This paper describes the development of a board equipped with a high-speed CPU and FPGA (Field Programmable Gate Array) to identify target through real-time image processing by acquiring target information through infrared image. We propose a CPU-FPGA combining architecture for CPU and FPGA selection and video signal processing, and also describe a controller design using FPGA to control infrared sensor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.10
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• pp.1467-1472
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• 2014

This paper study on powering characteristic on speed variation of propulsion system of prototype 8200 electric locomotive propulsion system through simulation modeling. For this purpose, it being applied in the field of railway IGBT (Insulated Gate Bipolar Transistor) elements are used. Converter was performed PLL (Phase-Locked Loop) control method that is used to control the phase and output voltage, and the inverter was carried an indirect vector control method to control the speed of traction motor. The results of simulation by modeling and experimental unit, we was confirmed that converter is controlled a unity power factor and output voltage by reference voltage. Also traction motor was controlled by indirect vector control and SVPWM inverter switching method very well.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.