• Journal of Technology Innovation
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• v.24 no.4
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• pp.1-26
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• 2016

The period after the PhD has a huge impact on the careers of researcher from a researcher lifecycle perspective. This is a turning point which student receives guidance from professor and become an independent researcher. Furthermore, they learn to develop ideas for independent research, apply for grants and manage a project; they also form expert networks in related filed and publish papers to share their findings. This study focuses on the period between earning doctoral degree and being employed as a stable position in university. This study starts from a research questions that asks which factors of postdoctoral experience affect research output. In this study, the paper performance, especially co-authorship of paper, of postdoctoral researchers was investigated. The cumulative advantage theory and Matthew effect were employed to shed a light on this research question. The empirical work is based on the Survey & Analysis of National R&D program in Korea conducted by Korea Institute of S&T Evaluation and Planning (KISTEP). The correlations between the research output and characteristics of postdoctoral experience were verified. These results are expected to contribute as new empirical evidences on investigating knowledge transfer activities of new PhDs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.