• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.473-480
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• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.87-96
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• 2021

Quantum computers will be a game-changer in various fields, such as cryptography and new materials. Quantum computer is quite different from the classical computer by using quantum-mechanical phenomena, such as superposition, entanglement, and interference. The main components of a quantum computer can be divided into quantum-algorithm, quantum-classical control interface, and quantum processor. Universal quantum computing, which can be applied in various industries, is expected to have more than millions of qubits with high enough gate accuracy. Currently, It uses general-purpose electronic equipment, which is placed in a rack, at room temperature to make electronic signals that control qubits. However, implementing a universal quantum computer with a low error rate requires a lot of qubits demands the change of the current control system to be an integrated and miniaturized system that can be operated at low temperatures. In this study, we explore the fundamental units of the control system, describe the problems and alternatives of the current control system, and discuss a future quantum control system.

• Journal of the Korea Convergence Society
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• v.7 no.5
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• pp.15-21
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• 2016

Recently the degree of integration of processor and developed rapidly. However, clock speed is not increased, a situation that increases the number of cores in the processor. In this paper, we analyze the performance of a typical Intel Xeon Phi of many core process used for the current operation accelerate. Utilizing the Quantum ESPRESSO, which was calculated using the FFTW library. By varying the number of ranks in MPI when running the benchmarks the performance Xeon Phi. The result shows a good performance in the handling of four job on one physical core. However, four or more to expand the number of MPI Rank is degraded. Through this convergence it was found to improve the performance of Quantum ESPRESSO. It is possible to check the hardware characteristics of the Xeon Phi.

• Progress in Superconductivity
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• v.5 no.1
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• pp.1-4
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• 2003

A five-year project for Nb-based single flux quantum (SFQ) circuits supported by Japan's Ministry of Economy Trade and Industry (METI) in Japan was started in September 2002. Since April 2003, the New Energy and Industrial Technology Development Organization (NEDO) has supported this Superconductor Network Device Project. The aim of the project is to improve the integration level of Nb-based SFQ circuits to several ten thousand Josephson junctions, in comparison with their starting integration level of only a few thousand junctions. Actual targets are a 20 GHz dual processor module for the servers and a 0.96 Tbps switch module for the routers. Starting in April 2003, the Nb project was merged with SFQ circuit research using a high-T$_{c}$ superconductor (HTS). The HTS research targets are a wide-band AD converter for mobile-phone base stations and a sampling oscilloscope for wide-band waveform measurements.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.5 no.1
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• pp.04-10
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• 1987

We consider a time sharing computer system with a single processor where tasks ofK different types arrive at the system according to independent time homogeneous Poisson processes from outside. A task, after given a quantum for processing, leaves the system, or changes the type and rejoins the system according to specified probabilitycs. While many existing priority time sharing models determine the priorities of tasks strictly by their service time requirements, this paper develops a new scheduling rule wherein the importances or urgencies in addition to the service time requirements of tasks are counted, by inposing an appropriate reward structure on the system. Also presented is the algorithm through which to determine the rankings of K types according to this new scheduling rule.

• The Journal of the Korea Contents Association
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• v.6 no.9
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• pp.28-41
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• 2006

Recently, Baruah et.al. proposed an optimal Pfair scheduling algorithm in the hard real-time multiprocessor environments, and several variants of it were presented. All these algorithms assume the fixed unit quantum size, and this assumption has two problems in the mode change environments. If the quantum size is too large, it results in the scheduling failure due to the decreased processor utilization. If it is too small, it increases the frequency of scheduling points, and it incurs the task switching overheads. In this paper, we propose several methods that determine the maximum quantum size dynamically such that the task set can be scheduled in the mode change environments.

• Electronics and Telecommunications Trends
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• v.35 no.7
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• pp.13-22
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• 2020

There is no denying that computing power has been a crucial driving force behind the development of artificial intelligence today. In addition, artificial intelligence (AI) semiconductors and computing systems are perceived to have promising industrial value in the market along with rapid technological advances. Therefore, success in this field is also meaningful to the nation's growth and competitiveness. In this context, ETRI's AI strategy proposes implementation directions and tasks with the aim of strengthening the technological competitiveness of AI semiconductors and computing systems. The paper contains a brief background of ETRI's AI Strategy #2, research and development trends, and key tasks in four major areas: 1) AI processors, 2) AI computing systems, 3) neuromorphic computing, and 4) quantum computing.

• Journal of Digital Convergence
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• v.12 no.9
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• pp.139-151
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• 2014

Quantum information and communication technology(QICT) holds out tremendous promise for efficiently solving some of the most difficult problems that are intractable on any present or future conventional computer. QICT is one of the most active research areas of modern science, attracting substantial funding that supports research groups at internationally leading academic institutions. To facilitate the progress of QICT research towards the commercialization, a roadmap needs to be formulated, providing some direction for the field with specific technical goals and elucidating interrelationships between approaches for synergistic solutions to obstacles within any one approach. In this paper, we suggest a brief version of roadmap for QICT research and give a discussion about the potential contribution of QICT in Korea industry.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.575-582
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• 2000

Because FIFO thread scheduling used in the existing multithreaded models does not consider locality in programs, it may result in the decrease of the performance of execution, caused by the frequent context switching overhead and delay of execution of relatively short frames. Quantum unit scheduling enhances the performance a little, but it still has the problems such as the decrease in the processor utilization and the longer delay due to its heavy dependency on the priority of the quantum units. In this paper, we propose shortest-frame-first(SFF) thread scheduling algorithm. Our algorithm selects and schedules the frame that is expected to take the shortest execution time using thread size and synchronization information analyzed at compile-time. We can estimate the relative execution time of each frame at compile-time. Using SFF thread scheduling algorithm on the multithreaded models, we can expect the faster execution, better utilization of the processor, increased throughput and short waiting time compared to FIFO scheduling.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.1-7
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• 2022

This paper aims to compare the mean object size of M/G/1/PS model with that of M/BP/1 model used in the web service. The mean object size is one of important measure to control and manage web service economically. M/G/1/PS model utilizes the processor sharing in which CPU rotates in round-robin order giving time quantum to multiple tasks. M/BP/1 model uses the Bounded Pareto distribution to describe the web service according to file size. We may infer that the mean waiting latencies of M/G/1/PS and M/BP/1 model are equal to the mean waiting latency of the deterministic model using the round robin scheduling with the time quantum. Based on the inference, we can find the mean object size of M/G/1/PS model and M/BP/1 model, respectively. Numerical experiments show that when the system load is smaller than the medium, the mean object sizes of the M/G/1/PS model and the M/BP/1 model become the same. In particular, when the shaping parameter is 1.5 and the lower and upper bound of the file size is small in the M/BP/1 model, the mean object sizes of M/G/1/PS model and M/BP/1 model are the same. These results confirm that it is beneficial to use a small file size in a web service.