• Title/Summary/Keyword: QVGA resolution

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ASG(Amorphous Silicon TFT Gate driver circuit)Technology for Mobile TFT-LCD Panel

  • Jeon, Jin;Lee, Won-Kyu;Song, Jun-Ho;Kim, Hyung-Guel
    • Journal of Information Display
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    • v.5 no.2
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    • pp.1-5
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    • 2004
  • We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA ($240{\times}320$) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

Design and Implementation of Depth Image Based Real-Time Human Detection

  • Lee, SangJun;Nguyen, Duc Dung;Jeon, Jae Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.212-226
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    • 2014
  • This paper presents the design and implementation of a pipelined architecture and a method for real-time human detection using depth image from a Time-of-Flight (ToF) camera. In the proposed method, we use Euclidean Distance Transform (EDT) in order to extract human body location, and we then use the 1D, 2D scanning window in order to extract human joint location. The EDT-based human extraction method is robust against noise. In addition, the 1D, 2D scanning window helps extracting human joint locations easily from a distance image. The proposed method is designed using Verilog HDL (Hardware Description Language) as the dedicated hardware architecture based on pipeline architecture. We implement the dedicated hardware architecture on a Xilinx Virtex6 LX750 Field Programmable Gate Arrays (FPGA). The FPGA implementation can run 80 MHz of maximum operating frequency and show over 60fps of processing performance in the QVGA ($320{\times}240$) resolution depth image.

Design and Implementation of High-Resolution Image Transmission Interface for Mobile Device (모바일용 고화질 영상 전송 인터페이스의 설계 및 구현)

  • Ahn, Yong-Beom;Lee, Sang-Wook;Kim, Eung-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.8
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    • pp.1511-1518
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    • 2007
  • As studies on ubiquitous computing are actively conducted, desire for various services, including image transmission storage, search and remote monitoring. has been expanding into mobile environment as well as to PCs. while CCTV (closed circuit TV) and un DVR (Digital video Recording) are used in places where security service such as intrusion detection system is required, these are high-end equipment. So it is not easy for ordinary users or household and small-sized companies to use them. Besides, they are difficult to be carried and camera solution for mobile device does not support high-quality function and provides low-definition of QVGA for picture quality. Therefore, in this study, design and implementation of embedded system of high-definition image transmission for ubiquitous mobile device which is not inferior to PC or DVR are described. To this end, usage of dedicated CPU for mobile device and design and implementation of MPEG-4 H/W CODEC also are examined. The implemented system showed excellent performance in mobile environment, in terms of speed, picture quality.

High Frame Rate CMOS Image Sensor with Column-wise Cyclic ADC (컬럼 레벨 싸이클릭 아날로그-디지털 변환기를 사용한 고속 프레임 레이트 씨모스 이미지 센서)

  • Lim, Seung-Hyun;Cheon, Ji-Min;Lee, Dong-Myung;Chae, Young-Cheol;Chang, Eun-Soo;Han, Gun-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.1
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    • pp.52-59
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    • 2010
  • This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.