• Journal of Power Electronics
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• v.15 no.6
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• pp.1524-1532
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• 2015

Conventional space vector pulse width modulation based asymmetrical dual inverter configuration produces high common mode voltage (CMV) variations. This CMV causes the flow of common mode current, which adversely affects the motor bearings and electromagnetic interference of nearby electronic systems. In this study, a simple and generalized carrier based pulse width modulation (PWM) technique is proposed for dual inverter configuration. This simple approach generates various continuous and discontinuous modulating signals based PWM algorithms. With the application of the discontinuous modulating signal based PWM algorithm to the asymmetrical dual inverter configuration, the CMV can be reduced with a slightly improved quality of output voltage. The performance of the continuous and discontinuous modulating signals based PWM algorithms is explored through both theoretical and experimental studies. Results show that the discontinuous modulating signal based PWM algorithm efficiently reduces the CMV and switching losses.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.6
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• pp.726-731
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• 2004

This paper proposes a pulse-width-modulation (PWM) controller design technique using intelligent digital redesign. Intelligent digital redesign is to convert a well-designed analog fuzzy-model-based controller into an equivalent pulse-amplitude-modulation (PAM) digital controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM intelligent digital controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of nonlinear artificial satellite system is included.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.1
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• pp.53-60
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• 2001

In many applications of power electronics, high frequency resonant inverters are used, and the PAM(Pulse Amplitude Modulation), PFM(Pulse Frequency Modulation) or PWM(Pulse Width Modulation) techniques are used to control the output power of resonant inverters. And the resonant inverters have to control the output frequency for the reliable operation under the variable load conditions. In this paper, a new switching scheme is proposed as a PWM control of resonant inverters. With the proposed method, it can be obtained that optimum resonant frequency and unity output displacement factor under the variable resonant frequency adaptively. The detail algorithm or the proposed PWM switching scheme and its output characteristics are discussed. And the veridity of the proposed method is confirmed with the experimental results.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.308-312
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• 2002

In this paper, EPLD(Erasable Programmable Logic Device) based induction motor drives with a SRP-PWM(Separatley Randomized Pulse Position PWM) is proposed. In the proposed RPWM (Random PWM), each of three phase pulses is located randomly in each switching interval. Based on the space vector modulation technique, the duty ratio of the pulses is calculated. To verify the validity of the proposed RPWM, the experimental study was tried. Along with the randomization of PWM pulses, the space vector modulation is also executed in the TMS320C31 DSP(Digital Signal Processor). The experimental results show that the voltage and switching noise harmonics are spread to a wide band area. Also, the performance of the proposed SRP-PWM and the conventional SVM-PWM are nearly the same from the viewpoing of the v/f constant control.

• Journal of Power Electronics
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• v.8 no.4
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• pp.363-370
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• 2008

In this paper, three kinds of PWM strategies for a three-phase current-fed dc/dc converter are proposed and compared in terms of losses and voltage transfer ratio. Each PWM strategy is described graphically and their switching losses are analyzed. With the proposed PWM C strategy, one turn-off switching of each bridge switch is eliminated to reduce switching losses under the same switching frequency. In addition, RMS current through the bridge switches is lowered by using parallel connection between two bridge switches and thus, conduction losses of the switches are reduced. Further, copper losses of the transformer are decreased due to the reduced RMS current of each transformer's winding. Therefore, total losses are minimized and the efficiency of the converter is improved by using the proposed PWM C strategy. Digital signal processor (DSP: TI320LF2407) and a field-programmable gate array (FPGA: EPM7128) board are used to generate PWM patterns for three-phase bridge and clamp MOSFETs. A 500W prototype converter is built and its experimental results verify the validity of the proposed PWM strategies.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.7
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• pp.539-548
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• 1989

This paper describes an instantaneous reactive power compensator aimed at the compensation of reactive power and current harmonics of a thyristor load. A new definition of the instantaneous reactive power consisting of both displacement of fundamental current and harmonic distortion current is proposed and the physical meaning is investigated from the viewpoint of an instantaneous power flow. The instantaneous reactive power is calculated from the feedback of instantaneous voltage, current and is compensated by the current controlled PWM converter connected in parallel with the load. The PWM converter operates as a high performance current control scheme, because adopts the excellent current controlled PWM technique based on the current deviation vector. Both simulation and experimental results show good compensating performances in steady and transient state.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.244-251
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• 2010

High speed motors have been widely used in industries to reduce system size and improve power conversion efficiency. However, the high speed motors sometimes suffer from core losses caused by PWM current ripple; noting that the phase inductance, $L_s$, of high speed motor is smaller than that of ordinary motors. In the proposed topology, three PWM inverters are connected in parallel through nine coupled inductors. Compared to the PWM current ripple of the conventional single inverter system, that of the proposed scheme can be conspicuously reduced without the voltage drop at the inductors. In this paper a theoretical analysis of the output voltage of the proposed topology is presented, and then the validity of the proposed method is verified by experimental results.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.7
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• pp.452-461
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• 2004

A novel multilevel PWM inverter is presented for the use of stand-alone photovoltaic power generation system. In appearance, it consists of three full-bridge modules and three cascaded transformers; therefore, the configuration of the proposed multilevel PW inverter is equal to that of a prior 11-level PWM inverter. Only the turn-ratio of a transformer and its corresponding switching function are different from each other. Owing to these differences, the proposed 19-level PWM inverter has two promising advantages. First, output voltage levels increase almost twofold. Consequently, it can generate more sinusoidal output voltage waveform. Second, due to a revised switching pattern, it lightens power imposed on the transformer, which is used for compensating output voltages with chopped pulses between steps. The validity of the proposed inverter system is verified by computer-aided simulations and experimental results based on a 1 ［kW］ prototype. The performance of the proposed 19-level PWM inverter is compared with the Prior 11-level PWM inverter and other counterparts.

• Journal of IKEEE
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• v.20 no.1
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• pp.103-106
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• 2016

PWM buck converters usually use a type-III error amplifier. Since this amplifier has a big capacitor with slow slew rate, they can generate an unintended large overshoot/undershoot at the output when a large load current change occurs. They can also respond slowly by varying the reference voltage. In order to increase battery lifetime, power supplies require a various range of load current and output voltage. PWM buck converter also should have a characteristic of both fast load response and reference tracking. This paper surveys a few recent techniques for reducing the settling time, and discusses their merits and limitations.