• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1592-1601
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• 1998

The growing use of unlicensed wireless systems has spurred interest in the 2.4 Ghz ISM band. In order to facilitate the efficient design of such systems, understandings of the propserties of radio wave propagation in buildings is necessary. Many authors have reported about statistical propagation models based on the extensive measurements in buildings. However, measurement based statistical analysis will not be enough for the optimum deployment of the communication systems in the specific building. Aviding expensive measurements in the individual buildings prior to installation, or adjustments afterwards, theoretical prediction models have been developed to predict the path loss and delay spread from the building floor plane. Predictions shows good agreements with measurements except for a few environments which was surrounded by heavy scatterers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.81-90
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• 2004

For deep submicron (DSM) very large scale integrated circuits (VLSI), it is well known that interconnects have become the dominant factor in determining the overall circuit performance. Buffer insertion is an effective technique of interconnect optimization. When a net has an excessive propagation delay, one or more buffers can be inserted to reduce the delay. Buffers also reduce the crosstalk between neighboring wires. While many conventional methods insert buffers net by net. we have developed new techniques in which buffer locations are simultaneously optimized for all nets. This is to avoid the difficulties in finding the right ordering of nets for buffer insertion. since several nets may compete for a buffer location. We also study buffer insertion with multiple fan-out nets to optimize critical path delay. Elmore delay model is used for delay calculation and the number of buffers for each net is determined to optimize the delay.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.3
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• pp.208-216
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• 2017

This paper presents the design method of an FMCW(frequency-modulated continuous-wave) altitude simulator which generates propagation delay signals according to target distances to test the radar altimeter. To improve the conventional RF method for creating delay signals, the simulator is designed by the RF-optics-RF method using optical delay lines. In addition, it is designed to simulate the Doppler shift and jamming that may occur in actual flight environment. In order to evaluate the performance of the developed simulator, the integration tests have been conducted with the radar altimeter. Through the test, we successfully verified the performance of the simulator.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.9
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• pp.720-727
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• 2008

Time delay effects on near-wall turbulent structures are investigated by performing a large-eddy simulation of a transient turbulent flow in a pipe. To elucidate the time delay effects on the near-wall turbulence, we selected the dimensionless acceleration parameter which was used in the previous study. Various turbulent statistics revealed the distinctive features of the delay. It was shown that the dynamic Smagorinsky model is valid to capture the alterations of the turbulence physics well. A dimensionless time for the responses of the flow quantities was introduced to give the detailed information on the delay of the nearwall turbulence. The conditionally-averaged flow fields associated with Reynolds shear stress producing events show that sweep and ejections are closely related to the delays of the turbulence production and the turbulence propagation toward the pipe center. The present study suggested that the enhanced anisotropy of the turbulence in the initial and transient stages would be a challenging problem to standard turbulence models.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.30 no.1
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• pp.1-11
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• 2022

The capacity of Jeju International Airport has reached its limit due to a surge in air traffic demand such as passengers and cargo and the continuous expansion of Low Cost Carriers (LCC). Despite COVID-19 that has began in November 2019, Jeju International Airport still has continuous demand in terms of passenger and cargo transportation. As a result, it is undeniable that the delay rate also unexpectedly increased as the air traffic volume at Jeju International Airport continued to increase. In this study, the correlation between Turnaround Time and delay rates of national airlines is analyzed based on past flight data at Jeju International Airport, and the cumulative delay time trend for sampled airlines is compared with Turnaround Time. Through this study, it is expected to contribute to securing aircraft operation efficiency and on-time by analyzing delays related to Turnaround Time at Jeju International Airport.

• ETRI Journal
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• v.22 no.4
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• pp.40-50
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• 2000

We apply a "sliding-window" Maximum Likelihood(ML) estimator to estimate traffic parameters On-Off source and develop a method for estimating stochastic predicted individual cell arrival rates. Based on these results, we propose a simple Connection Admission Control(CAC)scheme for delay sensitive services in broadband onboard packet switching satellite systems. The algorithms are motivated by the limited onboard satellite buffer, the large propagation delay, and low computational capabilities inherent in satellite communication systems. We develop an algorithm using the predicted individual cell loss ratio instead of using steady state cell loss ratios. We demonstrate the CAC benefits of this approach over using steady state cell loss ratios as well as predicted total cell loss ratios. We also derive the predictive saturation probability and the predictive cell loss ratio and use them to control the total number of connections. Predictive congestion control mechanisms allow a satellite network to operate in the optimum region of low delay and high throughput. This is different from the traditional reactive congestion control mechanism that allows the network to recover from the congested state. Numerical and simulation results obtained suggest that the proposed predictive scheme is a promising approach for real time CAC.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.4
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• pp.419-426
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• 1999

A novel motion analysis system is presented in this paper. The proposed system is inspired by processing functions observed in the fly visual system, which detects changes in input light intensities, determines motion on both the local and the wide-field levels. The system has several differences from conventional motion analysis system. First, conventional systems usually focused on matching similar feature or optical flow, but neural network is applied in this system. Back propagation is used by learning method, and Tine Delay Neural Network (TDNN) is also used as analysis method. Second, while conventional systems usually limited on only two frames of sequence, the proposed system accept multiple frames of sequence. The experimental results showed a 94.7% correct rate with a speed of 71.47 milli seconds for real and synthetic images.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2001.01a
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• pp.122-127
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• 2001

This study investigates the effectiveness of time delay neural networks(TDNN) for the time dependent prediction domain. Although it is well-known fact that the back-propagation neural network(BPN) performs well in pattern recognition tasks, the method has some limitations in that it can only learn an input mapping of static (or spatial) patterns that are independent of time of sequences. The preliminary results show that the accuracy of TDNN is higher than the standard BPN with time lag. Our proposed approaches are demonstrated by the stork market prediction domain.