• 전자공학회논문지A
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• 제32A권11호
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• pp.63-69
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• 1995

A novel programming architecture for antifuse FPGA(Field Programmable Gate Array) is described. This architecture prevents programming transistors from breakdown which occurs due to high voltage across the transistors during antifuse programming. Extra mask and processes can be avoided using this proposed architecture. To reduce the applied voltage across the terminals of programming transistors, different voltage ranges are supplied to vertical and horizontal tracks; between programming voltage Vp and Vp/2 for vertical tracks and between Vp/2 and 0V for horizontal tracks. Therefore, Maximum voltage across the programming transistors is half of the programming voltage and an designated antifuse can be programmed by applying maximum voltage for vertical track and minimum voltage for horizontal track while others are subjected to voltage difference below Vp/2.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of Electrical Engineering and Technology
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• 제11권2호
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• pp.329-337
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• 2016

With the increasing deployment of distributed generators in the distribution system, a very large search space is required when dynamic programming (DP) is applied for the optimized dispatch schedules of voltage and reactive power controllers such as on-load tap changers, distributed generators, and shunt capacitors. This study proposes a new optimal voltage and reactive power scheduling method based on dynamic programming with a heuristic searching space reduction approach to reduce the computational burden. This algorithm is designed to determine optimum dispatch schedules based on power system day-ahead scheduling, with new control objectives that consider the reduction of active power losses and maintain the receiving power factor. In this work, to reduce the computational burden, an advanced voltage sensitivity index (AVSI) is adopted to reduce the number of load-flow calculations by estimating bus voltages. Moreover, the accumulated switching operation number up to the current stage is applied prior to the load-flow calculation module. The computational burden can be greatly reduced by using dynamic programming. Case studies were conducted using the IEEE 30-bus test systems and the simulation results indicate that the proposed method is more effective in terms of saving electric charges and improving the voltage profile than loss minimization.

• 전자공학회논문지C
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• 제34C권8호
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• pp.64-70
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• 1997

This paper presents a parameter optimization method using evolutionary programming in voltage reference circuit because the designer must select appropriate parameter values of the circuit taking into consideration both powr voltage and temperature variation. In this paper, evolutionary programming is suggested as an approach for finding good parameters with which the reference voltage variation is small with respect to temperature variation. Simulation results. Simulation results show that this method is effective in circuit design.

• 대한전기학회논문지
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• 제43권6호
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• pp.869-876
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• 1994

This paper presents an efficient method to calculate voltage collapse point and to avoid voltage instability. To evaluate voltage stability in power systems, it is necessary to get critical loading points. For this purpose, this paper uses linear programming to calculate efficiently voltage collapse point. Also, if index value becomes larger than given threshold value, voltage stability is improved by compensation of reactive power at selected bus. This algorithm is verified by simulation on the IEEE 14-bus sample system.

• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.145-152
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• 2006

This paper presents a windows application for voltage sag analysis and effective data visualization. The developed Voltage Sag Analysis Tool (VSAT) was designed by using the Object-Oriented Programming (OOP) concept and C++ programming language. The VSAT provides basic functions for voltage sag analysis such as power flow analysis, short circuit analysis and stochastic analysis. In particular, the VSAT provides effective data visualization through computer graphics and animation. Analysis results are expressed realistically and intuitively on geographical display. The Graphic User Interface (GUI) of VSAT was designed specifically for voltage sag analysis. In this paper, the development and implementation of VSAT is presented. In order to demonstrate the capabilities of VSAT, it is used to analyze the Jeju Island power system in South Korea.

• 전기학회논문지
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• 제57권4호
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• pp.543-550
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• 2008

This paper proposes an voltage and reactive power control methodology, which is motivated towards implementation in the korea power system. The main voltage control devices are capacitor banks, reactor banks and LTC transformers. Effects of control devices are evaluated by local subsystem's cost computations. This local subsystem is decided by 'Tier' and 'Electrical distance' in the whole system. The control objective at present is to keep the voltage profile within constraints with minimum switching cost. A robust control strategy is proposed to make the control feasible and optimal for a set of power-flow cases that may occur important event from system. This studies conducted for IEEE 39-bus low and high voltage contingency cases indicate that the proposed control methodology is much more effective than PSS/E simulation tool in deciding switching of capacitor and reactor banks.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
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• pp.220-223
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• 2003

This paper presents VSCOPF(Votage Stability Constrained Optimal Power Flow) algorithm based on SLP(Successive Linear Programming) to interpret the large scale system. Voltage stability index used to this paper is L index to be presented by function form. The objective function consists of load shedding cost minimization. Voltage stability indicator constraint was incorporated in traditional OPF formulation. as well as the objective function and constraints are linearlized and the optimal problem is performed by SLP(Successive Linear Programming). In this paper, the effect of voltage stability limit constraint is showed in the optimal load curtailment problems. As a result, an optimal solution is calculated to minimize load shedding cost guaranteeing voltage security level. Numerical examples using IEEE 39-bus system is also presented to illustrate the capabilities of the proposed formulation.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.