• Title/Summary/Keyword: Programmable switch

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Resistive Memory Switching in Ge5Se5 Thin Films

  • Kim, Jang-Han;Hwang, Yeong-Hyeon;Chung, Hong-Bay
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.326-326
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    • 2014
  • It has been known since the mid 1960s that Ag can be photodissolved in chalcogenide glasses to form materials with interesting technological properties. In the 40 years since, this effect has been used in diverse applications such as the fabrication of relief images in optical elements, micro photolithographic schemes, and for direct imaging by photoinduced Ag surface deposition. ReRAM, also known as conductive bridging RAM (CBRAM), is a resistive switching memory based on non-volatile formation and dissolution of a conductive filament in a solid electrolyte. Especially, Ag-doped chalcogenide glasses and thin films have become attractive materials for fundamental research of their structure, properties, and preparation. Ag-doped chalcogenide glasses have been used in the formation of solid electrolyte which is the active medium in ReRAM devices. In this paper, we investigated the nature of thin films formed by the photo-dissolution of Ag into Ge-Se glasses for use in ReRAM devices. These devices rely on ion transport in the film so produced to create electrically programmable resistance states [1-3]. We have demonstrated functionalities of Ag doped chalcogenide glasses based on their capabilities as solid electrolytes. Formation of such amorphous systems by the introduction of Ag+ ions photo-induced diffusion in thin chalcogenide films is considered. The influence of Ag+ ions is regarded in terms of diffusion kinetics and Ag saturation is related to the composition of the hosting material. Saturated Ag+ ions have been used in the formation of conductive filaments at the solid electrolyte which is the active medium in ReRAM devices. Following fabrication, the cell displays a metal-insulator-metal structure. We measured the I-V characteristics of a cell, similar results were obtained with different via sizes, due to the filamentary nature of resistance switching in ReRAM cell. As the voltage is swept from 0 V to a positive top electrode voltage, the device switches from a high resistive to a low resistive, or set. The low conducting, or reset, state can be restored by means of a negative voltage sweep where the switch-off of the device usually occurs.

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Low-Latency Programmable Look-Up Table Routing Engine for Parallel Computers (병렬 컴퓨터를 위한 저지연 프로그램형 조견표 경로지정 엔진)

  • Chang, Nae-Hyuck
    • Journal of KIISE:Computing Practices and Letters
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    • v.6 no.2
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    • pp.244-253
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    • 2000
  • Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.

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Real-Time HIL Simulation of the Discontinuous Conduction Mode in Voltage Source PWM Power Converters

  • Futo, Andras;Kokenyesi, Tamas;Varjasi, Istvan;Suto, Zoltan;Vajk, Istvan;Balogh, Attila;Balazs, Gergely Gyorgy
    • Journal of Power Electronics
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    • v.17 no.6
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    • pp.1535-1544
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    • 2017
  • Advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. FPGA based HIL (Hardware-In-the-Loop) simulators have revolutionized control hardware and software development for power electronics. Common time step sizes in the order of 100ns are sufficient for simulating switching frequency current and voltage ripples. In order to keep the time step as small as possible, ideal switching function models are often used to simulate the phase legs. This often produces inferior results when simulating the discontinuous conduction mode (DCM) and disabled operational states. Therefore, the corresponding measurement and protection units cannot be tested properly. This paper describes a new solution for this problem utilizing a discrete-time PI controller. The PI controller simulates the proper DC and low frequency AC components of the phase leg voltage during disabled operation. It also retains the advantage of fast real-time execution of switch-based models when an accurate simulation of high frequency junction capacitor oscillations is not necessary.

UDP Flow Entry Management for Software-Defined Networking (사용자 정의 네트워크를 위한 사용자 데이터그램 프로토콜 플로우 엔트리 관리 기법)

  • Choi, Hanhimnara;Raza, Syed Muhammad;Kim, Moonseong;Choo, Hyunseung
    • Journal of Internet Computing and Services
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    • v.22 no.2
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    • pp.11-17
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    • 2021
  • Software-defined networking provides a programmable and flexible way to manage the network by separating the control plane from data plane. However, the limited switch memory restricts the number of flow entries in the flow table used to forward packets. This leads to flow table overflow and flow entry reinstallation, which severely degrade the network performance. Therefore, this paper proposes a comprehensive policy for timely eviction of inactive flow entries to optimally maintain flow tables usage. In particular, statistics of user datagram protocol flow entries are periodically sampled to enable the inactive entries to be evicted early. Through traffic-based experiments, we found that the proposed system reduces the number of overflow occurrences and flow entries reinstallation compared to the random and FIFO policies.

System Model-driven Conversion from PLC-based Systems to RTOS-based Systems (시스템 모델을 통한 PLC 기반 시스템의 RTOS 기반 시스템으로의 변환)

  • Kim, Je-Wung;Lim, Sung-Soo
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.3
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    • pp.13-26
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    • 2009
  • In this raper, We propose the alternative solution, RTOS-based system to replace the PLC 4hat has used the automation system for industrial processes. RTOS-based system is constructed the PC and RTOS as hardware and software. It overcomes the limit of PLC and guarantees the stability and reliability. Also, PC has better performance and cheaper than PLC when operating and constructing the system. For many manufactures, these benefits alone are all the reason they need to switch from PLC-based system to RTOS-based system. To use the RTOS-based System, the PLC program needs the conversion to the RTOS task. And how to transform is the most important issue. So, we propose conversion method through the system model. The system model defines the operation of each module as the task after the system divided into module. Because the system divided into modules can control, the performance and the functionality of system improve, and the system can deal with a problem easily when repairing and changing.

Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

  • Lee, DongSoo;Lee, Juri;Park, Hyung-Gu;Choi, JinWook;Park, SangHyeon;Kim, InSeong;Pu, YoungGun;Kim, JaeYoung;Hwang, Keum Cheol;Yang, Youngoo;Seo, Munkyo;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.1
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    • pp.126-142
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    • 2016
  • This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.