• Journal of the Korean Mathematical Society
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• v.32 no.1
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• pp.141-149
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• 1995

Let N denote the set of positive integers. Fix $d_1, d_2 \in N with d = d_1 + d_2$. Let X and Y be real random variables and let ${X_i : i \in N^d_1} and {Y_j : j \in N^d_2}$ be independent families of independent identically distributed random variables with $L(X) = L(X_i) and L(Y) = L(Y_j)$, where $L(\cdot)$ denote the law of $\cdot$.

• Bulletin of the Korean Mathematical Society
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• v.32 no.2
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• pp.221-231
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• 1995

Let $Z_1, Z_2, \ldots, Z_l$ be random set functions or intergrals. Then it is possible to discuss their products. In the case of random integrals, $Z_i$ is a random set function indexed y a family, $G_i$ say, of real valued functions g on $S_i$ for which the integrals $Z_i(g) = \smallint gdZ_i$ are well defined. If $g_i = \in g_i (i = 1, 2, \ldots, l) and g_1 \otimes \cdots \otimes g_l$ denotes the tensor product $g(s) = g_1(s_1)g_2(s_2) \cdots g_l(s_l) for s = (s_1, s_2, \ldots, s_l) and s_i \in S_i$, then we can defined $Z(g) = (Z_1 \times Z_2 \times \cdots \times Z_l)(g) = Z_1(g_1)Z_2(g_2) \cdots Z_l(g_l)$.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.671-676
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• 2003

In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14nS of multiplication speed of the $16{\times}16$ multiplier is obtained using $0.25\mu\textrm{m}$ CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.