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http://dx.doi.org/10.3745/KIPSTA.2003.10A.6.671

New High Speed Parallel Multiplier for Real Time Multimedia Systems  

Cho, Byung-Lok (순천대학교 전자공학과)
Lee, Mike-Myung-Ok (동신대학교 전기전자정보통신공학부)
Publication Information
The KIPS Transactions:PartA / v.10A, no.6, 2003 , pp. 671-676 More about this Journal
Abstract
In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14nS of multiplication speed of the $16{\times}16$ multiplier is obtained using $0.25\mu\textrm{m}$ CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.
Keywords
Parallel Multiplier; ASIC; Full Custom Design; SoC; IP; Multimedia; Communication System; FPA; CSA; CMOS; Pipelining Low Power;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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1 Young-in Kim and Jin-Ho Cho, 'An architecture for $32{\times}32 $ bit high speed parallel multiplier,' J. IEEK, Vol.31 B, No.10, pp.67-71, 1994   과학기술학회마을
2 IDEC, IDEC Cell Library Data Book, IDEC-D221, June, 2000
3 M. Lee, et al., 'IPs and SoC Design with Ultra-Low Power Real-Time Embedded 3-D Multimedia Chip,' CAD 및 VLSI 설계연구회 학술발표대회, 제1권, pp.47-52, 2002
4 N, Takagi, H. Yasuura and S. Yajima, 'High-speed VLSI multiplication algirithm with a redundant binary addition tree,' IEEE Trans. on Comput., Vol.C-34, No.9, pp.789-796, Sep., 1985   DOI   ScienceOn
5 Gensuke Goto, Atuski Inoue, and Ryoichi Ohe, 'A 4.1-ns compact 54 54-b multiplier utilizing sign-select booth encoders,' IEEE J. Solid-State Circuits, Vol.32, No.11, pp.1676-1681, Nov., 1997   DOI   ScienceOn
6 Deuk-kyung Kim, Kyung-Wook Shin, Yong-Surk Lee, and Moon-Key Lee, 'Area-time complexity analysis for optimal design of multibit recoding parallel multiplier,' J. IEEK, Vol.32 A, No.5, pp.71-80, 1995   과학기술학회마을
7 Kyung-Wook Shin, 'A high-speed complex multiplier based in redundant binary arithmetic,' J. IEEK, Vol.34 C, No.2, pp.29-37, 1997
8 B. I. Park, et al., 'A Regular Layout structured Multiplier based on Weighted Carry-Save Adders,' Proc. IEEE International Conference in Computer Design, pp.243-248, Oct., 1999   DOI
9 A. D. Booth, 'A signed binary multiplication technique,' J. Mechs. Appl. Math., Vol.4, No.2, pp.235-240, 1951   DOI
10 Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akibior Shimizu, and katuro Sasaki, 'A 4.4ns CMOS 54 54-b multiplier using pass-transistor multi-piexer,' IEEE J. Solid-State Circuits, Vol.30, No.30, pp.251-257, Mar., 1995   DOI   ScienceOn
11 Ahmad A. Hiasat, 'New efficient structure for a Modular Multiplier for RNS,' IEEE Trans. on Comput., Vol.49, No.2, pp.170-174, Feb., 2000   DOI   ScienceOn
12 C. S. Wallace, 'A suggestion for a fast multiplier,' IEEE Trans. on Electrin. Comput., Vol.EC-13, pp.14-17, 1964   DOI   ScienceOn
13 Yonmg Seok Lee, Geun Seon Hong, and Yong Deak Kim, 'Astudy on the design scheme of CSA array for the speed up of array multiplier,' J. IEEK. Vol.31 B, No.5, pp.73-80, 1994   과학기술학회마을