• ETRI Journal
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• v.29 no.6
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• Journal of Power Electronics
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• v.13 no.5
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• pp.787-797
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• 2013

Despite the advantages offered by multilevel inverters, one of the main drawbacks that prevents their widespread use is their circuit complexity as the number of power switches employed is usually high. This paper presents a new multilevel inverter topology with a considerable reduction in the number of power switches used through the switch-sharing approach. The fact that the proposed inverter applies two bidirectional power switches for sharing among the three phases does not prevent it from producing seven levels in the line-to-line output voltage waveforms. A modified scheme of space vector modulation via the application of virtual voltage vectors is developed to generate the PWM signals of the power switches. The performance of the proposed inverter is investigated through MATLAB/SIMULINK simulations and is practically tested using a laboratory prototype with a DSP-based modulator. The results demonstrate the satisfactory performance of the inverter and verify the effectiveness of the modulation method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.51-58
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• 2011

Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.532-534
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• 2004

단일서버 시스템에서 응용간 자원의 공정한 분배는 GPS(Generalized Processor Sharing)을 통친 실현될 수 있다. 그러나 다중서버시스템에서 GPS를 적용한다면, 각 서버 내에서의 공정성은 보장해 주지만, 시스템 관점에서의 공정성은 더 이상 보장되지 않는다. 본 논문에서는 멀티서버 시스템에서 시스템 관점에서의 공정성 보장을 위한 기법을 제시한다. 이 기법은 시스템에서 발생하는 각 서버의 잔여용량을 응용간 공정하게 분배하는 모델과 모델을 참조하여 실행하는 실제 스케줄링 알고리즘으로 구성된다 모델에서는 긴 시간동안 각 서버에서 발생하는 잔여용량의 사용을 관측하여, 향후 각 응용의 요청들에게 제공할 잔여용량 분배를 결정한다. 스케줄링 알고리즘은 모델에 의해 결정된 잔털용량 분배를 실제 각 응용들이 제대로 가져갈 수 있도록 제어한다. 실제 모델을 참조하여 공정 잔여용량 분배를 수행하는 스케줄링 알고리즘의 동작은 시뮬레이션을 통해 검증하였다.

• Journal of Korean Society for Quality Management
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• v.46 no.3
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• pp.411-424
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• 2018

Purpose: The purpose of this study is to improve submarine TACM launcher system safety device performance. Methods: In this study, EPLD(Electrically Programmable Logic Device) control and time sharing method to the safety device actuator motor and discrete signal processor in launch control panel were used to resolve unusual performance of safety system. Results: The result of this study are as follows; First, sporadic stopping of safety device actuator motor due to insufficient In-Rush current was resolved. Second, repeat of safety device condition as lock & release due to chattering for motor activating was resolved. Third, simultaneous release function for safety device actuator was available. Conclusion: The unusual performance of function for submarine TACM launcher system was overcame by applying EPLD control and time sharing method. The suggestions were proved by performance test in the pressure chamber. The results of this study enhanced survivability of ${\bigcirc}{\bigcirc}{\bigcirc}$ class submarine from enemy torpedo.

• Journal of KIEE
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• v.10 no.1
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• pp.35-42
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• 2000

An equivalent load sharing control based on the frequency and voltage droop concept for parallel operation of two three-phase Uninterruptible Power Supply (UPS) systems with no control interconnection lines is presented in this paper. First of all, due to the use of active power and reactive power as control variables, the characteristics of output powers according to amplitude and phase differences between output voltages of two UPS systems are analyzed. Secondly, simulation results under different line impedance demonstrate the feasibility of the wireless parallel operation control. Finally, experiments are presented to verify the theoretical discussion with two three-phase 20kVA UPS systems employed TMS320C32, a kind of real time digital signal processor (DSP).

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.121-124
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• 2000

Goal of this Paper is to design and develop core kernel components f3r single processor real-time system, which include real-time schedulers, synchronization mechanism, IPC, message passing, and clock & timer. The goal also contains the basic researches on dynamic load balancing and scheduling which provide mechanism for the distributed information processing and efficient resource sharing among various information appliances based on network.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.140-142
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• 2006

This paper represents a digital parallel control of a synchronous buck converter using a digital signal processor (DSP). The digital PWM and load sharing controller is implemented in the DSP TMS320F2812 and the experimental results are provided to show the feasibility of the digital synchronous buck regulator.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1867-1875
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• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.114-123
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• 1985

This is the second part of the four-part paper describing the development of a packet-switched computer network named the cORNET In this paper, following the first par paper that describes the concepts of the KORNET and the development of the network management center (NMC), wc present the design of the KORNET and the development of the network node processor (NNP) The initial configuration of the KORNET consists of three NNP's and one NMC. We have developed each NNP as a microprocessor-based (Mc68000) multiprocessor system, and implemented the NMC using a super-mini computer (Mv/8000) For the KORNET we use the virtual circuit (VC) method as the packet service strategy and the distributed adaptive routing algorithm to adapt efficiently the variation of node and link status. Also, we use a dynamic buffer management algorithm for efficient storage management. Thc hardware of the NNP system has been designed with emphasis on modularity so that it may be expanded esily . Also, the software of the NNP system has been developed according to the CCITT recommendations X.25, X.3, X.28 and X.29.