• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1259-1268
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• 2002

One of the major goals suggested in distributed system is to improve the performance of the system through the load balancing of whole system. Load balancing among systems improves the rate of processor utilization and reduces the turnaround time of system. In this paper, we design the rule of decision-making and information interchange based on knowledge based mechanism which makes optimal load balancing by sharing the future load state information inferred from past and present information of each nodes. The result of performance evaluation shows that utilization of processors is balanced, the processing time is improved and reliability and availability of systems are enhanced. The proposed mechanism in this paper can be utilized in the design of load balancing algorithm in distributed operating systems.

• ETRI Journal
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• v.39 no.1
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• pp.41-50
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• 2017

In connection-oriented data transport services, data loss can occur when a service experiences a problem in its end-to-end path. To resolve the problem promptly, the data transport systems providing the service must quickly modify their internal configurations, which are distributed among different locations within each system. The configurations are modified through a series of problem (event) handling procedures, which are carried out by multiple control processors in the system. This paper proposes a provisioning-to-signaling method for inter-control-processor messaging to improve the time efficiency of event processing. This method simplifies the sharing of the runtime event, and minimizes the time variability caused by the amount of event data, which results in a decrease in the latency time and an increase in the time determinacy when processing global events. The proposed method was tested for an event that required 4,000 internal path changes, and was found to lessen the latency time of global event processing by about 50% compared with the time required for general methods to do the same; in addition, it reduced the impact of the event data on the event processing time to about 30%.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10d
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• pp.259-262
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• 2006

라우터에서 세션간 출력링크 용량을 공정하게 분배하기 위해, Generalized Processor Sharing(GPS) 기반 공정큐잉 알고리즘들이 제안되었다. 이 알고리즘들은 대역폭 관점에서는 서버에 대기중인 각 세션들에게 공정한 서비스를 제공해 주지만, 지연 관점에서는 경계치 이하로 보장해 주는 서비스만 제공한다. 이로 인해 적은 양의 패킷을 생성하는 세션이라도 작은 지연으로 서비스 받고자 한다면, 큰 대역폭을 할당받아야 하는 문제가 발생한다. 이와 같이 지연과 대역폭이 결합됨으로 써 생기는 문제를 해결하고자 서비스커브 기반의 알고리즘이 제안되었지만, 이 알고리즘들은 서비스 지연과 대역폭간 제한된 분리밖에 지원하지 못한다. 본 논문에서는 서비스 지연과 대역폭을 분리하여 독립적으로 처리함으로 써, 각 세션에게 세션의 트래픽 특성에 맞게 서비스를 제공해 주는 지연-대역폭 정규화 모델을 제안한다. 이 모델은 서비스를 서비스 지연과 대역폭 측면에서 정의하고, 정의된 서비스를 서비스 가치(Value of Service: VoS)라는 개념을 통해 표현한다. 이 모델과 VoS개념을 이용하여 각 세션에게 지연-대역폭 관점에서 공정한 서비스를 제공하는 스케줄링 알고리즘을 제안한다. 이 알고리즘을 통해, 각 세션에게 지연-대역폭 관점에서 공정서비스, 전송률을 보장하는 서비스를 제공하려고 한다.

• ETRI Journal
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• v.30 no.4
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• pp.576-586
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• 2008

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.

• Journal of Power Electronics
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• v.7 no.3
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• pp.213-221
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• 2007

A digital state feedback control method for the current mode control of DC-DC converters is proposed in this paper. This approach can precisely achieve interleaved current sharing among the converter modules. As the controller design and system analysis are performed in the time domain, the proposed method can easily satisfy the required converter specification by using the pole placement technique. The digital state feedback controller in the continuous and discrete time domain is derived for the robust tracking control. For the verification of the proposed control scheme, a parallel module bi-directional converter in a prototype 42V/14V hybrid automotive power system, which is a design example in the continuous time domain, and a parallel module buck converter, which is a design example in the discrete time domain, are implemented using a TMS320F2812 digital signal processor (DSP).

• Journal of Information Processing Systems
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• v.1 no.1 s.1
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• pp.62-69
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• 2005

This paper presents a queuing analysis model of a PC-based software router supporting IPv6-IPv4 translation for residential gateway. The proposed models are M/G/1/K or MMPP-2/G/1/K by arrival process of the software PC router. M/G/1/K is a model of normal traffic and MMPP-2/G/1/K is a model of burst traffic. In M/G/1/K, the arriving process is assumed to be a Poisson process, which is independent and identically distributed. In MMPP-2/G/1/K, the arriving process is assumed to be two-state Markov Modulated Poisson Process (MMPP) which is changed from one state to another state with intensity. The service time distribution is general distribution and the service discipline of the server is processor sharing. Also, the total number of packets that can be processed at one time is limited to K. We obtain performance metrics of PC-based software router for residential gateway such as system sojourn time blocking probability and throughput based on the proposed model. Compared to other models, our model is simpler and it is easier to estimate model parameters. Validation results show that the model estimates the performance of the target system.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.1-7
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• 2022

This paper aims to compare the mean object size of M/G/1/PS model with that of M/BP/1 model used in the web service. The mean object size is one of important measure to control and manage web service economically. M/G/1/PS model utilizes the processor sharing in which CPU rotates in round-robin order giving time quantum to multiple tasks. M/BP/1 model uses the Bounded Pareto distribution to describe the web service according to file size. We may infer that the mean waiting latencies of M/G/1/PS and M/BP/1 model are equal to the mean waiting latency of the deterministic model using the round robin scheduling with the time quantum. Based on the inference, we can find the mean object size of M/G/1/PS model and M/BP/1 model, respectively. Numerical experiments show that when the system load is smaller than the medium, the mean object sizes of the M/G/1/PS model and the M/BP/1 model become the same. In particular, when the shaping parameter is 1.5 and the lower and upper bound of the file size is small in the M/BP/1 model, the mean object sizes of M/G/1/PS model and M/BP/1 model are the same. These results confirm that it is beneficial to use a small file size in a web service.

• Journal of KIISE:Databases
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• v.33 no.6
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• pp.563-577
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• 2006

A stream processor uses resource sharing method for efficient of limited resource in multiple continuous queries. The previous methods process aggregate queries to consist the level structure. So insert operation needs to reconstruct cost of the level structure. Also a search operation needs to search cost of aggregation information in each size of sliding windows. Therefore this paper uses linear structure for optimization of sliding window aggregations. The method comprises of making decision, generation and deletion of panes in sequence. The decision phase determines optimum pane size for holding accurate aggregate information. The generation phase stores aggregate information of data per pane from stream buffer. At the deletion phase, panes are deleted that are no longer used. The proposed method uses resources less than the method where level structures were used as data structures as it uses linear data format. The input cost of aggregate information is saved by calculating only pane size of data though numerous stream data is arrived, and the search cost of aggregate information is also saved by linear searching though those sliding window size is different each other. In experiment, the proposed method has low usage of memory and the speed of query processing is increased.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.