• Title/Summary/Keyword: Processor Reuse Information.

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The Study of an Object-Oriented Macro Assembler for Next-Generation Microprocessors (차세대 마이크로프로세서를 위한 어셈블러의 객체화에 대한 연구)

  • Jeong, Tae-Ui;Lee, Ji-Yeong;Lee, Gwang-Yeop;Lee, Yong-Seok
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.3
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    • pp.804-811
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    • 1999
  • The object-oriented methods are being rapidly accepted as the solution for the software crisis. Object-oriented systems are composed of the integration of independent object modules; their merits are such that it is possible to reuse objects already developed, and that, when changes are required, modifications are restricted to some independent objects such that their affects to other objects are so little. In this paper, we deal with the macro assembler for next-generation microprocessors which has the merits of object methods. Whenever a microprocessor is newly developed, new assembler should be developed or the existing assembler be modified. In the former, it leads to the loss of time and money by the repeated developments, and, in the latter, it causes the problem of inefficient productivity since other modules are to be analyzed for the affections followed by modifications of one module, especially in the existing assemblers. To resolve these problems, the object-oriented macro assembler suggested in this paper consists of independent objects separable such that it shows reusability and reduces the inefficient productivity by minimizing the affects to other objects. Moreover, the object-oriented macro assembler integrates a macro pre-processor into an assembler, and uses automata for analyzing input streams to reduce the compile time.

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Design and Implementation of Component Storages for Developing Component-Based Game Engines (컴포넌트 기반 게임엔진 개발을 지원하는 컴포넌트 저장소의 설계 및 구현)

  • Song Eui Cheol;Kim Jung Jong
    • The KIPS Transactions:PartD
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    • v.12D no.2 s.98
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    • pp.267-274
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    • 2005
  • New game softwares usually have much similarities with old one in the sense of properties and procedures. But nevertheless, the development could be duplicated several times without referencing or reusing of others. In addition, because there is no standardized process about the game engine, the products generated by other software development processes are difficult to understand and to reuse. Therefore, the enterprise developing new game software newly analyze and design although it is same process as the old one. This paper proposes the improved process of the game engine, analysis of structures and relations, classification of the class and the module and their combination methods, implementation of storage, and processor model to apply the component based development method to the game engine.

Design and Implementation of JPP(JNI Preprocessor) (JPP(JNI 전처리기)의 설계 및 구현)

  • Lee, Chang-Hwan;O, Se-Man
    • The KIPS Transactions:PartA
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    • v.9A no.1
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    • pp.129-136
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    • 2002
  • JNI is a linkage method to other languages such as C/C++ which enables the Java to do the platform-dependent specific tasks and also, it can be used to reuse the existing libraries and programs. However, the complex and difficult steps are required to use JNI and it is Inconvenient to manipulate Java source and C/C++ source separately. We design and implement the JPP (Java Preprocessor) that enables the Java source and C/C++ source to handle in a same source file and reduces the required steps so as to use JNI easily.

A VLSI Array Processor Architecture for High-Speed Processing of Full Search Block Matching Algorithm (완전탐색 블럭정합 알고리즘의 고속 처리를 위한 VLSI 어레이 프로세서의 구조)

  • 이수진;우종호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.4A
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    • pp.364-370
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    • 2002
  • In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

The Flexible Design Architecture for a Continuous Packet Connectivity Protocol on High Speed Packet Access Platform (고속 패킷 접속 규격 플랫폼 기반 연속적인 패킷 연결 프로토콜의 유연한 구조 설계)

  • Kwon, Hyun-Il;Kim, Kyung-Ho;Lee, Chung-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.30-35
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    • 2009
  • In this paper, we propose the flexible design architecture for a continuous packet connectivity (CPC) Protocol among additional features of 3GPP HSPA+. In order to meet a practical intellectual property (IP) reuse and the developing time reduction design goals, we utterly take a CPC protocol into account to be realized by reusing digital signal processor (DSP) IP of the proven high speed packet access (HSPA) platform with the minimum hardware modification and addition. Based on the Teak series DSP, the proposed CPC protocol is divided into discontinuous transmit and receive mode, CPC manager, and interface with the proven HSPA platform. According to the regularized verification flow for wireless cellular communication applications, the proposed CPC protocol has been verified in various test scenarios.

Performance Analysis of a Cell - Cluster - Based Call Control Procedure for Wireless ATM Networks (셀집단화 방식에 근거한 무선 ATM 호제어절차의 성능분석)

  • Cho, Young-Jong;Kim, Sung-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.7
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    • pp.1804-1820
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    • 1997
  • In this paper, an efficient call control procedure is presented for next generation wireless ATM networks and its performance is mathematically analyzed using the open queueing network. This procedure is based on a new scheme called as the cell clustering. When we use the cell clustering scheme, at the time that a mobile connection is admitted to the network, a virtual cell is constructed by choosing a group of neighboring base stations to which the call may probabilistically hand over and by assigning to the call a collection of virtual paths between the base stations. Within a microcell/picocell environment, it is seen that the cell clustering can support effectively a very high rate of handovers, provides very high system capacity, and guarantees a high degree of frequency reuse over the same geographical region without requiring the intervention of the network call control processor each time a handover occurs. But since mobiles, once admitted, are free to roam within the virtual cell, overload condition occurs in which the number of calls to be handled by one base station to exceed that cell site's capacity of radio channel. When an overload condition happens, the quality of service is abruptly degraded. We refer to this as the overload state and in order to quantify the degree of degradation we define two metrics, the probability of overload and the normalized average time spent in the overload state. By using the open network queueing model, we derive closed form expressions for the maximum number of calls that can be admitted into the virtual cell such that the two defined metrics are used as the acceptance criteria for call admission control.

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