• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2006.06a
• /
• pp.249-250
• /
• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Korean Journal of Optics and Photonics
• /
• v.12 no.1
• /
• pp.10-16
• /
• 2001

A new digital serrodyne (DS) signal processor for the close-loop fiber optic gyroscope was designed and implemented. It is based on a new algorithm that can solve the remaining problems of the existing digital serrodyne processing by utilizing a new modulation wavefonn. The algorithm was implemented in an FPGA and tested. Theoretical limit and experimental value of the random walk were measured to be 2.6 and 3.3 deg/hr/$\sqrt{Hz}$, respectively. And drift of the processor is smaller than that by Shupe's effect.effect.

• Proceedings of the KIEE Conference
• /
• 2011.07a
• /
• pp.1296-1297
• /
• 2011

This paper deals with a power-hardware-in-the loop simulation (PHILS) of permanent magnet synchronous generator (PMSG) type wind power generation system (WPGS) using a real hardware which consists of a motor generator set with motor drive, real time digital simulator (RTDS), and back-to-back converter. A digital signal processor (DSP) controls the back-to-back converter connected between the back-to-back converter and the RTDS. The proposed PHILS can effectively be applied to demonstrate the operational characteristics of PMSG type WPGS under grid connection.

• Journal of Korea Multimedia Society
• /
• v.3 no.3
• /
• pp.309-319
• /
• 2000

The purpose of a parallel scheduling under a multiprocessor environment is to carry out the scheduling with the minimum synchronization overhead, and to perform load balance for a parallel application program. The processors calculate the chunk of iteration and are allocated to carry out the parallel iteration. At this time, it frequently accesses mutually exclusive global memory so that there are a lot of scheduling overhead and bottleneck imposed. And also, when the distribution of the parallel iteration in the allocated chunk to the processor is different, the different execution time of each chunk causes the load imbalance and badly affects the capability of the all scheduling. In the paper. we investigate the problems on the conventional algorithms in order to achieve the minimum scheduling overhead and load balance. we then present a new parallel loop scheduling algorithm, considering the locality of the data and processor affinity.

• ETRI Journal
• /
• v.36 no.1
• /
• pp.124-133
• /
• 2014

To speed up data-intensive programs, two complementary techniques, namely nested loops parallelization and data locality optimization, should be considered. Effective parallelization techniques distribute the computation and necessary data across different processors, whereas data locality places data on the same processor. Therefore, locality and parallelization may demand different loop transformations. As such, an integrated approach that combines these two can generate much better results than each individual approach. This paper proposes a unified approach that integrates these two techniques to obtain an appropriate loop transformation. Applying this transformation results in coarse grain parallelism through exploiting the largest possible groups of outer permutable loops in addition to data locality through dependence satisfaction at inner loops. These groups can be further tiled to improve data locality through exploiting data reuse in multiple dimensions.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1655-1666
• /
• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2380-2388
• /
• 2015

A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

• Journal of Positioning, Navigation, and Timing
• /
• v.6 no.4
• /
• pp.195-203
• /
• 2017

A 2U cube satellite called SNUGLITE has been developed by GNSS Research Laboratory in Seoul National University. Its main mission is to perform actual operation by mounting dual-frequency global positioning system (GPS) receivers. Its scientific mission aims to observe space environments and collect data. It is essential for a cube satellite to control an Earth-oriented attitude for reliable and successful data transmission and reception. To this end, an attitude estimation and control algorithm, Attitude Determination and Control System (ADCS), has been implemented in the on-board computer (OBC) processor in real time. In this paper, the Extended Kalman Filter (EKF) was employed as the attitude estimation algorithm. For the attitude control technique, the Linear Quadratic Gaussian (LQG) was utilized. The algorithm was verified through the processor in the loop simulation (PILS) procedure. To validate the ADCS algorithm in the ground, the experimental verification via a single axis Hardware-in-the-loop simulation (HILS) was used due to the simplicity and cost effectiveness, rather than using the 3-axis HILS verification (Schwartz et al. 2003) with complex air-bearing mechanism design and high cost.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.7 no.9
• /
• pp.105-111
• /
• 1999

The paper presents development of a Hardware-In-the-Loop simulation (HILS) system for the purpose of testing performance, stability, and reliability of an electronic power steering system(EPS). In order to realistically test an EPS by the proposed HILS apparatus, a simulated uniaxial dynamic rack force is applied physically to the EPS hardware by a pnumatic actuator. An EPS hardware is composed of steering wheel &column, a rack & pinion mechanism, andas motor-driven power steering system. A command signal for a pneumatic rack-force actuator is generated from the vehicle handling lumped parameter dynamic model 9software) that is simulated in real time by using a very fast digital signal processor. The inputs to the real-time vehicle dynamic simulation model are a constant vehicle forward speed and from wheel steering angles driven through a steering system by a driver. The output from a real-time simulation model is an electric signal that is proportional to the uniaxial rack force. The vehicle handling lumped parameter dynamic model is validated by a fully nonlinear constrained multibody vehicle dynamic model. The HILS system simulation results sow that the proposed HILS system may be used to realistically test the performance stability , and reliability of an electronic power steering system is a repeated way.

• Journal of Sensor Science and Technology
• /
• v.6 no.2
• /
• pp.95-105
• /
• 1997

A new open-loop signal processing technique of digital phase tracking is known to have a Potential to solve the problems in the open-loop processor such as limited dynamic range, dependence on the optical intensity fluctuations, and dependence on gain fluctuations of signal path. But new problems with digital phase tracking must be solved before it can be a useful signal processing method. In this paper, barriers to the success of the digital phase tracking such as harmonics content, phase difference, amplitude variations of the phase modulation(PM) signal, bandwidth limit of the signal path, and the implementation of the mixer, are pointed out and their effects on the performance of the signal processor are analyzed to calculate the requirements of the signal processor for $1{\mu}rad$-grade FOG.