• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1337-1342
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• 1990

This paper deals with control system design strategy for electrolmaginetic suspension (E.M.S.) system. For a successful control of E.M.S. system, the nature of E.M.S. system is deeply studied in the view point of non-linear, open-loop unstable, time-varying, non-minimum phase system. To find a special control treatment for E.M.S. system, analyses and simulations for various models are carried out. As one of the successful candidates, adaptive control concept is introduced and sample hardware system using digital signal processor is implemented.

• Journal of Power Electronics
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• v.12 no.1
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• pp.88-97
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• 2012

This paper presents a method for the digital control of a high power factor AC/DC converter employing the power balance control technique to achieve a fast response of the output voltage control. To avoid the effects of an output voltage ripple in the voltage control loop, the average output voltage is sampled and used as a feedback signal for the output voltage controller. The proposed control technique was verified by simulations using MATLAB/Simulink and its implementation was realized by a dsPIC30F4011 digital signal processor to control a CUK topology AC/DC converter with a 48V output voltage and a 250 W output power. The experimental results agree with the simulation results. The proposed control technique achieves a fast transient response with a lower line current distortion than is achieved when using a conventional proportional-integral controller and the power balance control technique with the conventional sampling method.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.475-480
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• 2000

A new positioning mechanism with Parallel type actuator using piezoelectric material and with dual type actuators using voice coil motor (VCM) and piezoactuator is proposed for optical disk drive or near-field recording type drive, and high speed position and vibration control are investigated. Parallel type bimorph piezoactuator is used as a fine motion actuator with self-sensing technique, which allows a piezoelectric material to concurrently sense and actuate in a closed loop frame work, and positive position feedback control algorithm is adopted to further control residual vibration. For positioning control of VCM, PID control algorithm is adopted.

• The Journal of Korean Association of Computer Education
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• v.18 no.2
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• pp.71-81
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• 2015

In the EISC processor, the Instruction Queue (IQ) supporting LERI folding and loop buffering occupies roughly 20% of real estate, and its efficient utilization is a key for performance. This paper presents an architectural enhancement for the IQ utilization with return address stack (RAS) in the EISC processor. The proposed architecture eliminates the RAS corruption from the wrong-path, taking advantage of shallow pipeline. In experiments, a 4-entry RAS reduces the number of IQ flushes by up to 58.90% over baseline, and an 8-entry RAS by up to 61.28%. The experiments show up to 3.47% performance improvement with 8-entry RAS and up to 3.15% performance improvement with 4-entry RAS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.9
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• pp.1212-1218
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• 2014

For OBC (On-Board Charger) and LDC (Low DC-DC Converter) used as essential power conversion systems of PHEV (Plug-in Hybrid Electric Vehicle), system performance is required as well as reliability, which is need to protect the vehicle and driver from various faults. While current development processor is sufficient for embodying functions and verifying performance in normal state during development of prototypes for OBC and LDC, there is no clear method of verification for various fault situations that occur in abnormal state and for securing stability of vehicle base, unless verification is performed by mounting on an actual vehicle. In this paper, a CCM (Charger Converter Module) was developed as an integrated structure of OBC and LDC. In addition, diverse fault situations that can occur in vehicles are simulated by a simulator to artificially inject into power conversion system and to test whether it operates properly. Also, HILS (Hardware-in-the-Loop Simulation) is carried out to verify whether LDC is operated properly under power environment of an actual vehicle.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1886-1900
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• 2018

This paper proposes a confronting feedback control structure and controllers for positive output elementary super lift Luo converters (POESLLCs) working in discontinuous conduction mode (DCM). The POESLLC offers the merits like high voltage transfer gain, good efficiency, and minimized coil current and capacitor voltage ripples. The POESLLC working in DCM holds the value of not having right half pole zero (RHPZ) in their control to output transfer function unlike continuous conduction mode (CCM). Also the DCM bestows superlative dynamic response, eliminates the reverse recovery troubles of diode and retains the stability. The proposed control structure involves two controllers respectively to control the voltage (outer) loop and the current (inner) loop to confront the time-varying ON/OFF characteristics of variable structured systems (VSSs) like POESLLC. This study involves two different combination of feedback controllers viz. the proportional integral controller (PIC) plus sliding mode controller (SMC) and the fuzzy logic controller (FLC) plus SMC. The state space averaging modeling of POESLLC in DCM is reviewed first, then design of PIC, FLC and SMC are detailed. The performance of developed controller combinations is studied at different working states of the POESLLC system by MATLAB-Simulink implementation. Further the experimental corroboration is done through implementation of the developed controllers in PIC 16F877A processor. The prototype uses IRF250 MOSFET, IR2110 driver and UF5408 diodes. The results reassured the proficiency of designed FLC plus SMC combination over its counterpart PIC plus SMC.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.10
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• pp.805-812
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• 2013

The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.27-34
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• 2006

This paper has implemented a very small($1.4{\times}2.8[Cm^2]$) 13.56[MHz] RFID reader ensuring machine ID recognition correctly in a noise space of Tag-to-Reader within 3Cm. For operation of the RFID system, at first, this paper has designed the loop antenna of a reader and the fading model of back-scattering on microwave propagation following to 13.56[MHz] RFID Air Interface ISO/IEC specification. Secondly, this paper has proposed the automatically path selected RF switching circuit and the firmware operation relationship by measuring and analyzing the very small RFID RF issues. Finally, as a very small reader main body, this paper has shown the DSP board and software functions made for extraction of $1{\sim}2$ machine ID information and error prevention simultaneously with carrying of 13.56[MHz] RFID signals that the international standard specification ISO/IEC 18000-3 defined.