• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.377-383
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• 2002

An all-digital closed-loop (ADCL) signal processor for an open-loop FOG was developed to replace the analog circuitry of a Digital Phase Tracking (DPT) signal processor with new digital circuitry. When the ADCL signal processor without a stabilizer for fiber phase modulator (FPM) was attached to the FOG, temperature drift of FOG was about 0.26$\mu$rad/$^{\circ}C$, which makes the FOG unusable in medium or higher-grade applications. This drift was due to variations of phase modulation amplitude and phase delay of the FPM. The stabilizer controls its phase modulation amplitude and phase delay by regulating the ratio of harmonics of the FOG output. Thus, the stabilizer reduces the drift of the FOG to negligible.

• Korean Journal of Optics and Photonics
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• v.8 no.5
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• pp.426-430
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• 1997

A signal processor is implemented to verify the possibility of a closed-loop signal processing for the open-loop fiber-optic gyroscope (FOG). As an all-digital implementation of phase tracking scheme, it does analog-to digital conversion of the detector output and signal processing all-digitally thereafter for a noise-immune FOG signal processor. It has a potential of 36-bits resolution in the $2\pi$ range which is best in the number and sets no limit in the magnitude of the phase shift. The new signal processor was tested on an all-fiber gyroscope and turned out to have a resolution of $3\mu$rad(corresponds to 0.74 deg/hr), which is good enough to measure the Earth's rotation rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.159-166
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• 2013

This paper proposes an efficient loop accelerator for a motion estimation specific instruction-set processor. ME algorithms in nature contain complex and multiple loop operations. To support efficient hardware (HW) loop operations, this paper introduces four loop instructions and their specific HW architecture. The simulation results show that the proposed loop accelerator can reduce about 29% average instruction cycles for ME early-termination schemes compared with typical implementation having a combination of compare and conditional jump instructions. The proposed loop accelerator of the motion estimation specific instruction-set processor can significantly reduce the number of program memory accesses and greatly save power consumption. Hence, it can be quite suitable for low power and flexible ME implementation.

• Proceedings of the Optical Society of Korea Conference
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• 2004.02a
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• pp.296-297
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• 2004

A Signal processor for the open-loop fiber optic gyroscope(FOG) is equipped with a stabilizer to reduce the error due to drift of fiber phase modulator (FPM). The stabilizer is designed to be operated to maintain the ratio of amplitude and phase between harmonics in the FOG signal. When FPM stabilizer is used, the temperature drift of FOG is reduced to less than 0.5 deg/hr in change of 20$^{\circ}C$.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1465-1469
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• 2003

In general satellite verification process, the AOCS (Attitude & Orbit Control Subsystem) should be verified through several kinds of verification test which can be divided into two major category like FBT (Fixed Bed Test) and polarity test. And each test performed in different levels such as ETB (Electrical Test Bed) and satellite level. The test method of FBT is to simulate satellite dynamics with sensors and actuators supported by necessary environmental models in ETB level. The VDS (Vehicle Dynamic Simulator) try to make the real situation as possible as the on-board processor will undergo after launch. The purpose of FBT test is to verify that attitude control logic function and hardware interface is designed as expected with closed loop simulation. The VDS is one of major equipments for performing FBT and consists of software and hardware parts. The VDS operates in VME environments with target board, several commercial boards and custom boards based on the VxWorks real time operating system. In order to make time synchronization between VDS and satellite on-board processor, high reliable semaphore was implemented to make synchronization with the interrupt signal from on-board processor. In this paper, the real-time operating environment used on VDS equipment is introduced, and the hardware and software configurations of VDS summarized in the systematic point of view. Also, we try to figure out the operational concept of VDS and AOCS verification test method with close-loop simulation.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.112-116
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• 1992

In this paper, a fuzzy logic controller(FLC) is designed for the pointing loop of the spin-stabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. The pointing loop of the spin-stabilized platform using FLC has better performance of step responses than a proportional controller in case of same loop hain through the software simulation and the experiment of implemented hardware.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.2
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• pp.91-98
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• 2012

Power Quality (PQ) signal such as sag, swell, harmonics, and impulsive transients are the major issues in the operations of the power electronics based devices and microprocessor based equipments. The effectiveness of wavelet based denoising techniques and recognizing different power quality events with noise has been presented in this paper. The algorithms involved in the noisy PQ recognition system are the wavelet based denoising and the back propagation neural networks. Also, in order to verify the real-time performances of the noisy PQ recognition systems under the noisy environments, SIL(Software In the Loop) and PIL(Processor In the Loop) were carried out, resulting in the excellent recognition performances.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.22-28
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• 2016

Multi-loop control of a boost converter needs a current-sensing circuit to detect the inductor current. Current sensorless multi-loop control reduces the cost, size and weight of the converter. The Luenberger observer (LO) is widely used to estimate the inductor current for current sensorless control of a switching converter. However, the design of the LO-based sensorless multi-loop control has not been well presented, so far. In this paper, a closed-loop characteristics evaluation method is proposed to design an LO-based current sensorless multi-loop control for boost converters. Simulations show evaluations of the closed-loop characteristics. Practical experiments on a digital processor confirm the simulations.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.56-66
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• 1993

In this paper, a fuzzy logic controll(FLC) is designed for the pointing loop of the spinstabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. Through the simulation and the experiment, it can be seen that the designed FLC shows better performance than a conventional controller using the same loop gain.