• Title/Summary/Keyword: Processor Array

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Partitioning Technique for Equivalents of Power System (전력계통 등가화를 위한 지역분할기법)

  • Han, Soung-Ho;Rim, Seong-Jeong;Yoon, Yong-Han;Kim, Jae-Chul
    • Proceedings of the KIEE Conference
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    • 1993.07a
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    • pp.112-114
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    • 1993
  • This paper presents a partitioning technique for equivalent models to large scale power system. The proposed partitioning technique is utilized by using a heuristic approach based on distributed array processor and the coherent groupings of generator buses. In this paper the reduced Ward-PV method considering the characteristics of buses is used to equivalent models of external system. The technique is demonstrated on New England system with 39 buses, 46 lines and 10 generators.

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Implementation of An Embedded Platform-Based ATSC Mobile Broadcasting Multiplexer (임베디드 플렛폼 기반 미국향 모바일방송 다중화기 설계 및 구현)

  • Kwon, KiWon;Park, KyungWon;KIm, HyunSik;Lee, YounSung
    • IEMEK Journal of Embedded Systems and Applications
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    • v.6 no.2
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    • pp.93-99
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    • 2011
  • In this paper, an ATSC(Advanced Television Standard Committee)-M/H(Mobile/Handheld) multiplexer is designed and implemented using an embedded Linux based hardware platform. The ATSC-M/H multiplexer is composed of a CPU(Central Processor Unit), an FPGA(Field-Programmable Gate Array), ASI(Asynchronous Serial Interface)/SMPTE310(Society of Motion Picture and Television Engineers310) interface board, and a GPS(Global Position System) clock processing block. The main functions of the ATSC-M/H multiplexer executed in the CPU and FPGA are described. The operation of the ATSC-M/H multiplexer is verified by processing its broadcast signal on a commercial receiver analyzer.

Implementation of Real-Time Data Logging System for Radar Algorithm Analysis (레이다 알고리즘 분석을 위한 실시간 로깅 시스템 구현)

  • Jin, YoungSeok;Hyun, Eugin
    • IEMEK Journal of Embedded Systems and Applications
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    • v.16 no.6
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    • pp.253-258
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    • 2021
  • In this paper, we developed a hardware and software platform of the real-time data logging system to verify radar FEM (Front-end Module) and signal-processing algorithms. We developed a hardware platform based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and implemented firmware software to verify the various FEMs. Moreover, we designed PC based software platform to control radar logging parameters and save radar data. The developed platform was verified using 24 GHz multiple channel FMCW (Frequency Modulated Continuous Wave) in an environment of stationary and moving targets of chamber room.

Technology Trends in Communication Payload for the Broadband LEO Satellite Constellation (저궤도 군집 통신위성 탑재체 기술 동향)

  • Uhm, M.S.;Chang, D.P.;Lee, B.S.
    • Electronics and Telecommunications Trends
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    • v.37 no.3
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    • pp.41-51
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    • 2022
  • This article presents an overview of the key technologies in the communications payload of broadband LEO satellite communications systems. In recent years, new developments have been realized for LEO satellite communications. SpaceX's Starlink, a technology leader in this field, offers premium services with satellites carrying in-house developed communications payloads. OneWeb, Amazon, Telesat, and Boeing are also developing LEO satellite communications payloads. The communications payload consists of user link antennas, inter-satellite link communications equipment, feeder link antennas, and a digital processor. Highly sophisticated technologies of compact active phased array antennas for generating multiple hopping beams and light laser communication equipment for ultra-high-speed inter-satellite communication will be applied to next- generation payloads.

Parallel algorithm of global routing for general purpose associative processign system (법용 연합 처리 시스템에서의 전역배선 병렬화 기법)

  • Park, Taegeun
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.4
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    • pp.93-102
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    • 1995
  • This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.

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PASS: A Parallel Speech Understanding System

  • Chung, Sang-Hwa
    • Journal of Electrical Engineering and information Science
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    • v.1 no.1
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    • pp.1-9
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    • 1996
  • A key issue in spoken language processing has become the integration of speech understanding and natural language processing(NLP). This paper presents a parallel computational model for the integration of speech and NLP. The model adopts a hierarchically-structured knowledge base and memory-based parsing techniques. Processing is carried out by passing multiple markers in parallel through the knowledge base. Speech-specific problems such as insertion, deletion, and substitution have been analyzed and their parallel solutions are provided. The complete system has been implemented on the Semantic Network Array Processor(SNAP) and is operational. Results show an 80% sentence recognition rate for the Air Traffic Control domain. Moreover, a 15-fold speed-up can be obtained over an identical sequential implementation with an increasing speed advantage as the size of the knowledge base grows.

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The Bit-Map Trip Structure for Giga-Bit Forwarding Lookup in High-Speed Routers (고속 라우터의 기가비트 포워딩 검색을 위한 비트-맵 트라이 구조)

  • Oh, Seung-Hyun;Ahn, Jong-Suk
    • Journal of KIISE:Information Networking
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    • v.28 no.2
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    • pp.262-276
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    • 2001
  • Recently much research for developing forwarding table that support fast router without employing both special hardware and new protocols. This article introduces a new forwarding data structure based on the software to enable forwarding lookup to be penormed at giga-bit speed. The forwarding table is known as a bottleneck of the routers penormance due to its high complexity proportional to the forwarding table size. The recent research that based on the software uses a Patricia trie and its variants. and also uses a hash function with prefix length key and others. The proposed forwarding table structure construct a forwarding table by the bit stream array in which it constructs trie from routing table prefix entries and it represents each pointer pointing the child node and the associated forwarding table entry with one bit The trie structure and routing prefix pointer need a large memory when representing those by linked-list or array. but in the proposed data structure, the needed memory size is small enough since it represents information with one bit. Additionally, by use a lookup method that start searching at desired middle level we can shorten the search path. The introduced data structure. called bit-map trie shows that we can implement a fast forwarding engine on the conventional Pentium processor by reducing the backbone routing table fits into Level 2 cache of Pentium II processor and shortens the searching path. Our experiments to evaluate the performance of proposed method show that this bit-map trie accomplishes 5.7 million lookups per second.

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Improvement of Signal Processing Circuit for Inspecting Cracks on the Express Train Wheel (고속 신호처리 회로에 의한 고속철도 차륜검사)

  • Hwang, Ji-Seong;Lee, Jin-Yi;Kwon, Suk-Jin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.579-584
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    • 2008
  • A novel nondestructive testing (NDT) system, which is able to detect a crack with high speed and high spatial resolution, is urgently required for inspecting small cracks on express train wheels. This paper proposes an improved signal processing circuits, which uses the multiple amplifying circuits and the crack indicating pulse output system of the previous scan-type magnetic camera. Hall sensors are arrayed linearly, and the wheel is rotated with static speed in the vertical direction to sensor array direction. Each Hall voltages are amplified, converted and immediately operated by using, amplifying circuits, analog-to-digital converters and $\mu$-processor, respectively. The operated results, ${\partial}V_H/{\partial}t$, are compared with a standard value, which indicates a crack existence. If the ${\partial}V_H/{\partial}t$ is larger than standard value, the pulse signal is output, and indicates the existence of crack. The effectiveness of the novel method was verified by examine using cracks on the wheel specimen model.

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Fiber-Optic Interferometric Sensor System for Remote Sensing and Its Application to Pressure Sensing (원격 측정을 위한 간섭형 광섬유 센서 시스템과 그의 압력 센서 응용)

  • Yeh, Yun-Hae;Jung, Hwan-Soo;Lah, Doh-Sung
    • Journal of Sensor Science and Technology
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    • v.6 no.3
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    • pp.172-179
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    • 1997
  • This paper describes a multiplexed-multivariate fiber-optic interferometric sensor system with remote sensing capability. Signal processor of the implemented sensor system is designed as a digital fringe counter that is well adapted to the signal processing of the remote fiber-optic Fabry-Perot interferometric sensor array. By summing up the reported optical data of the optical fiber, a guideline for choosing the optical effect suitable for a specific measurand is presented. As an example, a pressure sensing device that utilizes the strain-optic effect of the optical fiber by attaching it onto a stainless steel diaphragm of which diameter is 4.3 cm, is built and attached to the sensor system. The changes in optical phase difference of the fiber-optic Fabry-Perot interferometric press ure sensor while filling a water tank 2 meters high, was counted by the half-fringe counting signal processor. Test results showed that the measurement error is less than ${\pm}3.6\;cm$ over the measured range of 2 meters.

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A Study on the Development of Gear Transmission Error Measurement System and Verification (기어 전달오차 계측 시스템 개발 및 검증에 관한 연구)

  • Moon, Seok-Pyo;Lee, Ju-Yeon;Moon, Sang-Gon;Kim, Su-Chul
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.20 no.12
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    • pp.136-144
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    • 2021
  • The purpose of this study was to develop and verify a precision transmission error measurement system for a gear pair. The transmission error measurement system of the gear pair was developed as a measurement unit, signal processing unit, and signal analysis unit. The angular displacement for calculating the transmission error of the gear pair was measured using an encoder. The signal amplification, interpolation, and transmission error calculation of the measured angular displacement were conducted using a field-programmable gate array (FPGA) and a real-time processor. A high-pass filter (HPF) was applied to the calculated transmission error from the real-time processor. The transmission error measurement test was conducted using a gearbox, including the master gear pair. The same test was repeated three times in the clockwise and counterclockwise directions, respectively, according to the load conditions (0 - 200 N·m). The results of the gear transmission error tests showed similar tendencies, thereby confirming the stability of the system. The measured transmission error was verified by comparing it with the transmission error analyzed using commercial software. The verification showed a slight difference in the transmission error between the methods. In a future study, the measurement and analysis method of the developed precision transmission error measurement system in this study may possibly be used for gear design.