• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1078-1084
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• 2001

In this paper, fuzzy-ARTMAP neural network is applied for compensating the nonlinearity of satellite communication channel. The fuzzy-ARTMAP is made of using fuzzy logic and ART neural network. By a match tracking process with vigilance parameter, fuzzy ARTMAP neural network achieves a minimax learning rule that minimizes predictive error and maximizes generalization. Thus, the system automatically learns a minimal number of recognition categories, or hidden units, to meet accuracy criteria. Simulation studies are performed over satellite nonlinear channels. The performance of proposed fuzzy-ARTMAP equalizer is compared with MLP-basis equalizers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10A
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• pp.1639-1644
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• 2001

Two decision feedback equalizer structures employing recurrent neural network (RNN) used for non-linear channels with severe intersymbol interference (ISI) and non-linear distortion are proposed in this paper, which skillfully put the traditional decision feedback structure for linear channels equalization into RNN, replace decision feedback signal with training signal in the learning process and adaptively adjust the learning step. Simulative results of the first type of two new equalizer structures have shown that it has better equalization performances than traditional recurrent neural network equalizer (RNNE) under the same condition.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.10
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• pp.59-64
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• 2008

In this paper an adjustable linear gain equalizer which is operated from 6GHz to 18GHz in order to apply wideband RF circuit System is proposed and fabricated on $Al_2O_3$ substrate using thin film process. An adjustable linear gain equalizer is proposed to T type circuit and designed to aim on variable slope $-7dB{\sim}-13dB$ using the PIN Diode

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.635-639
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• 2016

In the devices used in the microwave frequency band, the gain decreases as the frequency increases due to the parasitic component. To compensate for these characteristics, a linear gain equalizer with an opposite slope is needed in wideband systems, such as those used for electronic warfare. In this study, a linear gain equalizer that can be used in the 18 ~ 40GHz band is designed and fabricated. Circuit design and momentum design (optimizations) were carried out to reduce the errors between design and manufacturing. A thin film process is used to minimize the parasitic components within the implementation frequency band. A sheet resistance of 100 ohm/square was employed to minimize the wavelength variation due to the length of the thin film resistor. This linear gain equalizer is a structure that combines a quarter wavelength-resonator on a series microstrip line with a resistor. All three 1/4 wavelength short resonators were used. The fabricated linear gain equalizer has a loss of more than -5dB at 40GHz and a 6dB slope in the 18 ~ 40GHz band. By using the manufactured gain equalizer in a multi-stage connected device such as an electronic warfare receiver, the gain flatness degradation with increasing frequency can be reduced.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.46-53
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• 2011

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. The CCI is a critical factor which affects occurring data errors in a cell, when surrounding cells are programed. We derived a characteristic equation for CCI considering write procedure of data that is similar with signal equalizing. The model considers the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. We verify the proposed equalizer comparing with the measured data of 1-block MLC NAND flash memory. As the simulation result, the equalizer shows an error correction ratio about 60% under 20nm NAND process.

• Korean Journal of Optics and Photonics
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• v.11 no.6
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• pp.447-451
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• 2000

In this paper, an adaptive equalizer which has been widely used in communication channel and high-density storage system was adopted to mitigate ISI and improve BER generated during storage and retrieval process of the digital holographic memory system. Our experimental results show that the BER performance with an adaptive equalizer is improved about 19.6% on average compared to the binary-decision process by global thresholding. lding.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.97-103
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• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5A
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• pp.441-449
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• 2011

Sample timing offset (STO) and carrier frequency offset (CFO) are caused by inter-symbol interference (ISI), inter-carrier interference (ICI) and phase error in orthogonal frequency division multiplexing (OFDM) system. OFDM characteristic is sensitive about STO and CFO. So when ICI occurs, compensation is hard and complex equalizer is needed. In this paper, we propose an effective correction method using feedback process with pilot and synchronization symbol. After feedback with estimated value in frequency domain, STO and CFO are corrected by control sample & and holder and oscillator. As a result of simulation, we confirm that STO and CFO can be corrected without equalizer through feedback.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.