• 제목/요약/키워드: Process Routing

검색결과 382건 처리시간 0.036초

An Efficient Routing Algorithm Considering Packet Collisions in Cognitive Radio Ad-hoc Network (CR Ad-hoc Network에서 패킷 충돌을 고려한 효율적인 경로탐색 알고리즘)

  • Kim, Jin-Su;Choi, Jun-Ho;Shin, Myeong-Jin;Lee, Ji-Seon;Yoo, Sang-Jo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제38B권9호
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    • pp.751-764
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    • 2013
  • In cognitive radio ad-hoc networks, common control channel overload and packet collisions are occured due to indiscriminate broadcasting of control packets. So that the path reliability is reduced and control channel is easily saturated. In this paper, we propose a new routing algorithm considering the probability of appearance of primary user and channel status of neighbor nodes. When the source node needs to transmit a data packet to the destination, it performs route discovery process by exchanging control messages using a control channel in ADOV CR Ad-hoc networks. If any intermediate node doesn't have common data channel with previous node to transmit data, it doesn't rebroadcast control packet. And if it has common data channels with previous node, each node determines channel contribution factor with the number of common channels. Based on the channel contribution factor, each node performs different back-off broadcasting. In addition, each node controls control packet flooding by applying to proposed advanced mode using such as number of available channels and channel stability. With the proposed method, the number of control packets to find the data transmission path and the probability of collision among control packets can be decreased. While the path reliability can be increased. Through simulation, we show that our proposed algorithm reduces packet collisions in comparison with the traditional algorithm.

Design and Implementation of Location Based Seamless Handover for IEEE 802.11s Wireless Mesh Networks (IEEE 802.11s 무선 메쉬 네트워크를 위한 위치 기반 핸드오버의 설계 및 구현)

  • Lee, Sung-Han;Yang, Seung-Chur;Kim, Jong-Deok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제13권10호
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    • pp.2004-2010
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    • 2009
  • The characteristic of the backbond for distribution service in WMNs(Wireless Mesh Networks) is that WMNs has multiple links connected to mesh points and dynamic routing protocol such as AODV to establish routing paths. When the terminal is communicating with the service through new AP, mobile nodes can resume communication by setting only the link between new AP and mobile node in the case of existing WLANs, but WMNs needs path establishment process in multihop networks. Our goal in this paper is to support the seamless communication service by eliminating path establishment delay in WMNs. We present the method that eliminates the handover latency by predicting the location of handover using GPS information and making the paths to their destination in advance. We implement mesh nodes using embedded board that contains proposed handover method and evaluate performance of handover latency. Our experiment shows that handover delay time is decreased from 2.47 to 0.05 seconds and data loss rate is decreased from 20~35% in the existing method to 0~10% level.

Different Heterogeneous IoT Data Management Techniques for IoT Cloud Environments (IoT 클라우드 환경을 위한 서로 다른 이기종의 IoT 데이터 관리 기법)

  • Cho, Sung-Nam;Jeong, Yoon-Su
    • Journal of Convergence for Information Technology
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    • 제10권12호
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    • pp.15-21
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    • 2020
  • Although IoT systems are used in a variety of heterogeneous environments as cloud environments develop, all IoT devices are not provided with reliable protocols and services. This paper proposes an IoT data management technique that can extend the IoT cloud environment to an n-layer multi-level structure so that information collected from different heterogeneous IoT devices can be efficiently sorted and processed. The proposed technique aims to classify and process IoT information by transmitting routing information and weight information through wireless data link data collected from heterogeneous IoT devices. The proposed technique not only delivers information classified from IoT devices to the corresponding routing path but also improves the efficiency of IoT data processing by assigning priority according to weight information. The IoT devices used in the proposed technique use each other's reliable protocols, and queries for other IoT devices locally through a local cloud composed of hierarchical structures have features that ensure scalability because they maintain a certain cost.y channels of IoT information in order to make the most of the multiple antenna technology.

Scheduling Algorithm using DAG Leveling in Optical Grid Environment (옵티컬 그리드 환경에서 DAG 계층화를 통한 스케줄링 알고리즘)

  • Yoon, Wan-Oh;Lim, Hyun-Soo;Song, In-Seong;Kim, Ji-Won;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • 제47권4호
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    • pp.71-81
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    • 2010
  • In grid system, Task scheduling based on list scheduling models has showed low complexity and high efficiency in fully connected processor set environment. However, earlier schemes did not consider sufficiently the communication cost among tasks and the composition process of lightpath for communication in optical gird environment. In this thesis, we propose LSOG (Leveling Selection in Optical Grid) which sets task priority after forming a hierarchical directed acyclic graph (DAG) that is optimized in optical grid environment. To determine priorities of task assignment in the same level, proposed algorithm executes the task with biggest communication cost between itself and its predecessor. Then, it considers the shortest route for communication between tasks. This process improves communication cost in scheduling process through optimizing link resource usage in optical grid environment. We compared LSOG algorithm with conventional ELSA (Extended List Scheduling Algorithm) and SCP (Scheduled Critical Path) algorithm. We could see the enhancement in overall scheduling performance through increment in CCR value and smoothing network environment.

DRAM Package Substrate Using Aluminum Anodization (알루미늄 양극산화를 사용한 DRAM 패키지 기판)

  • Kim, Moon-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제47권4호
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    • pp.69-74
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    • 2010
  • A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

Design of 4Kb Poly-Fuse OTP IP for 90nm Process (90nm 공정용 4Kb Poly-Fuse OTP IP 설계)

  • Hyelin Kang;Longhua Li;Dohoon Kim;Soonwoo Kwon;Bushra Mahnoor;Panbong Ha;Younghee Kim
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • 제16권6호
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    • pp.509-518
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    • 2023
  • In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm2).

Short-Time Production Scheduling and Parts Routing for Flexible Assembly Lines (유연한 조립 시스템의 단기 생산 스케듈링과 라우팅에 관한 연구)

  • Sin, Ok-Geun
    • The Transactions of the Korea Information Processing Society
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    • 제2권6호
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    • pp.823-830
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    • 1995
  • A reactive piloting policy for Flexible Assembly Lines (FAL) is proposed, where the sequencing of the operations as well as the assignment of tasks to manipulators are not predetermined but driven by the actual state of the FAL For all work-in-process coming from a manipulator, the next destination is determined by minimizing a temporal criterion taking into account the time needed to reach the destination, the load of the manipulator to reach, the durati on of the operation to be completed in the destination manipulator, and the availability of product components in this manipulator. The purpose of proposed piloting policy is to manufacture a given quantity of products as rapidly as possible by balancing the amount of work allocated to manipulators and to reduce the efforts required for scheduling the production of short series of diversified products. After introducing the characteristics of assembly processes and FAL modelization, the proposed algorithm is evaluated by simulations. The simulations of the proposed algorithm showed satisfactory results.

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The Development of an End-Effector in Automated Pavement Crack Sealer and Technical Feasibility Analysis (도로면 크랙실링 자동화 장비 말단장치의 요구성능 분석을 통한 설계·제작 및 기술적 타당성 분석)

  • Lee, Jeong-Ho;Lee, Won-Jae;Yoo, Hyun-Seok;Kim, Young-Suk
    • KSCE Journal of Civil and Environmental Engineering Research
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    • 제32권4D호
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    • pp.367-376
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    • 2012
  • Crack sealing is a maintenance technique commonly used to prevent water and debris penetration and reduce future degradation in pavement. The conventional crack sealing operations are, however, dangerous, costly, and labor-intensive. Automating crack sealing will improve productivity and quality, and offer safety benefits by getting worker off the road. During the last two decades, several teleoperated and machine-vision assisted systems have been developed to automate the overall process of routing and sealing pavement cracks. However, the developed systems have not been commonly used in the construction sites because of the technical problems. Especially, the performance of end-effector, related to the productivity and quality improvement, is very important factor to improve the practical use of the developed systems. The main objective of this research is to develop an end-effector in automated pavement crack sealing machine and to analyze the technical feasibility of the developed end-effector.

Robust Placement Method for IR Drop in Power Gating Design (파워 게이팅 설계에서 IR Drop에 견고한 셀 배치 방법)

  • Kwon, Seok Il;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • 제53권6호
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    • pp.55-66
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    • 2016
  • Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.

A Virtual Object Hosting Technology for IoT Device Controlling on Wireless AP's (무선 인터넷 공유기에서 사물 인터넷 장치 제어를 위한 가상 오브젝트 호스팅 기술 연구)

  • Yang, Jinhong;Park, Hyojin;Kim, Yongrok;Choi, Jun Kyun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제39C권2호
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    • pp.164-172
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    • 2014
  • Recently, as the number of IoT (Internet of Things) devices for personal or home intelligence increases, the need for unified control and cooperative utilization is required. This paper presents a novel idea, proposes methods for virtualizing Internet of Things (IoT) devices and hosting them on the home AP instead of relying on a cloud service or purchasing a new device to do so. For this, the process and profile of the IoT gadgets need to be virtualized into JavaScript-based objects. Then, to execute and control the instances of the virtualized IoT objects on the wireless AP, a novel instance management method and their interfaces are designed. The implementation and performance section demonstrates the proposed system's stability and operability by showing the stress test results while the wireless AP is running for its wireless routing.