• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.71-71
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• 2012

Memory 반도체 Test공정에서 사용되는 Probe Card의 Probing Area가 넓어지면서 종래에 사용되던 Cantilever제품의 사용이 불가능하게 되고, MEMS공정을 사용한 새로운 형태의 Advanced제품이 시장에 출현을 하였다. MEMS형의 제품은 다수의 Micro Spring을 MLC(Multi Layer Ceramic)위에 MEMS 공정을 사용하여 생성하는 방식으로서 MLC는 좁은 지역에 다수의 Pin을 생성 할 수 있는 공간을 만들어 주며, 또 다른 이유는 전기적 특성인 임피던스를 맞추고 다수의 Pin의 압력에 의하여 생기는 하중을 Ceramic기판으로 지탱하기 위한 목적도 있다. 이에 MLC와 같은 전기적 특성을 임피던스를 맞춘 RF-CPCB를 사용하여 작은 면적에 다수의 Pin접합이 가능한 방법을 마련한 후, 이 RF-PCB를 부착하여 Pin의 하중을 받는 Wafer와 유사한 열팽창을 갖는 Substrate를 사용하여 MLC를 대체하여 다양한 온도 조건에서 사용이 가능하며, 복잡하고 공정비가 많이 드는 MEMS 공정에 의한 일괄 Micro Spring 생성 공정을 전주 도금 또는 2D방식의 도금 Pin으로 대체하였으며, Probe Card의 중요한 물리적 특성인 Pin들의 정렬도를 마련하기 위해 Photo Process를 사용한 Wafer로 만든 Wafer Pin Array Frame을 사용하여 2D 제작 Pin을 일괄 또는 부분 접합이 가능한 방법으로 Probe Array Head를 제작하여 이들을 부착하여 Probe Array Head를 이전의 MEMS공정 방법에 비해 쉽고 빠르게 만들어 probe Card를 제작 할 수 있게 되었다.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.109-114
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• 2019

In this paper, simulations of S-parameter and characteristic impedance for the probe pin are performed and its high-frequency performance is analyzed. The probe pins are arranged with one signal pin in the center and four ground pins on the top, bottom, left and right sides. The insertion loss and return loss of the probe pin are calculated while increasing the separation between the probe pins to 0.35 mm, 0.40 mm, and 0.50 mm, respectively. It is confirmed that the probe pin has different features of the insertion loss due to its periodic resonance phenomenon. Effect of the characteristic impedance on pitch and assignment of the probe pin is also analyzed. It is verified that there are a number of ground pins whose characteristic impedance is close to 50 Ω.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.120.1-120.1
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• 2017

최근 첨단 기능화 되고 있는 반도체의 회로는 증가하고 칩의 브릿지도 점점 증가하고 있다. 반면에 제품은 소형화되고 회로폭은 미세화 하고, 피치는 감소하고 있다. 이에 회로의 정확한 검사를 위해서는 Probe Pin의 신뢰성을 중요시하게 되면서 도금기술의 고품질화가 요구되는 실정이다. 본연구에서는 Probe Pin과 내구성과 금도금 피막의 두께를 확보하여 국산 반도체 검사장비 시장을 선도 할 수 있도록 금도금피막의 두께와 밀착성 확보와 함께 굽힘시험시 박리와 크랙방지를 위한 기초연구를 수행하고자 하였다.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.24 no.6
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• pp.647-652
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• 2015

A probe pin is a key component of LED inspection equipment. The probe pin makes contact with the LED electrodes and supplies an electric current. Because the mechanical and electrical homogeneity of the probe surface affects the service life and reliability, its characterization is essential. For this study, the hardness was measured using a micro-Vickers hardness test. Moreover, the thicknesses of the plating at different locations and the elemental compositions were examined using an FE-SEM. The uniformity of the plating was found to be acceptable because palladium was detected consistently throughout the tested domain. In addition, the hardness of the surface was determined to be higher than that of the typical palladium range, which is attributed to the use of undercoated nickel.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.225-226
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• 2010

• Korean Journal of Materials Research
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• v.22 no.10
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• pp.545-551
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• 2012

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The $SnO_2$ phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< $150^{\circ}C$). Further oxidation to $SnO_2$ is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.7
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1071-1072
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• 2015

MFC를 사용하여 기본 GUI를 제작하고 X축과 Y축, Z축에 모터를 장착하여 X축과 Y축으로 이동해 원하는 곳에 CCD카메라를 이동시켜 자동으로 영상을 확보 할 수 있도록 제작하며 Z축의 모터를 사용하여 CCD카메라와 광학 조명을 조절해 깨끗한 영상을 획득하여 Probe Pin의 Top과 Side를 검사한다.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.97-103
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• 2024

In this paper, the difference between the S-parameter and the characteristic impedance according to the structural change of the fine pitch coaxial socket was analyzed. A pitch of the probe pin was applied to 0.20mm, and ground pins of different conditions were placed on each of the five signal pins. Insertion loss and reflection loss were analyzed for the coaxial socket of normal structure and the two sockets of the proposed structure. In addition, the difference in characteristic impedance was analyzed using time domain reflectometry. Through the analysis, it was confirmed that the characteristic impedance was improved applying the new structures of the socket at the same pitch

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.177-186
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• 2012

In this paper, we propose a design method that the crosstalk of probe connector pins satisfy the limitation of -30 dB. The parameters(inductance and capacitance) were extracted in the grid-structured probe connector pin system, and it is shown that the new parameters are easily calculated with increasing ground pin numbers using the previously calculated parameters. In addition, the crosstalk reduction algorithm by employing more grounds around the signal pin has been suggested, and it is confirmed that the suggested method is quite effective especially for the reduction of inductive couplings. Finally, we suggested the correlation between the pitch and the length of the pins to satisfy the crosstalk limitation of -30 dB with the given number of ground pins, which will be quite useful when design a probe connector pin system.