• Title/Summary/Keyword: Printed wiring boards

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A Study on the Physical Separation Characteristics of Valuable Metals from the Waste Printed Wiring Boards (물리적 처리에 의한 폐 컴퓨터 기판으로부터 유가금속의 분리선별 특성 연구)

  • 현종영;채용배;정수복
    • Resources Recycling
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    • v.11 no.1
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    • pp.9-18
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    • 2002
  • Printed wiring boards(PWBs) of the obsolete computers are composed of various organic and inorganic compounds as well as metals and alloys. As convinced that the valuable metals obtained from the PWBs are effectively utilized as secondary resources when recovered by economical methods, in this study, an investigation for characterizing the physical separation techniques is conducted. For the recovery of them, the sockets and chips dismantled from PWBs by scraping and residual resin boards are subjected to the appropriate separation processes according to the physical properties of each part. In the case of crushed socket scraps size ranged from -2.36 mm to +1.18 mm, approximately 97 wt% of the product obtained by magnetic separation consists of metallic compounds. In the case of chip scraps, 97% of Fe-Ni alloy and 95% of Cu metal are recovered by the combined process of air classification and dry magnetic separation in the size range from -2.36 mm to +0.15 mm. Ball milling is adopted in order to improve the removal efficiency of the thin-printed metallic materials on the residual resin boards and approximately 77% of Cu metal is recovered by zigzag separation after ball milling.

THE RECENT TREND OF BUILD-UP PRINTED CIRCUIT BOARD TECHNOLOGIES

  • Takagi, Kiyoshi
    • Journal of the Korean institute of surface engineering
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    • v.32 no.3
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    • pp.289-296
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    • 1999
  • The integration of the LSI has been greatly improved and the circuit patters on the LSI are becoming finer line and pitch. The high-density electronic packaging technology is improved. In order to realize the high-density packaging technology, the density of the circuit wiring of the printed circuit boards have also been more dense. The build-up process multilayer printed circuit board technology have a lot of vias, possibilities of the finer conductor wirings and have a freedom of capabilities of wiring design. The build-up process printed circuit boards have the wiring rules which are the pattern width: $100-20\mu\textrm{m}$, the via hole diameter: $100-50\mu\textrm{m}$. There three kinds of build-up processes as far materials and hole drilling. In this paper, the recent technology trends of the build-up printed circuit board technologies are described.

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Multi-Layer Printed Wiring Board with Built-In Soldering Heater and 3D Implementation of Dynamically Reconfigurable Highly Parallel Processors

  • Fujika, Yoshichika;Lee, Doo-Yong
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.104.2-104
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    • 2001
  • In the intelligent integrated systems, the delay time must be reduced using highly parallel processors, as well as high throughput performance. In this paper, we propose a new concept for building 3D highly parallel processors using multi-layer printed wiring boards with built-in soldering heater (BISH-PWB). The proposed BISH is realized with the long and narrow cupper wiring pattern on the internal layer in the terminal pattern area. Based on the linearity of the cupper resistance vs. temperature, we can measure the BISH, temperature and its calorific value from the heater voltage and current measurements. If we provide the BISH temperature control systems for each BISH, selective multi-point soldering can be realized with same ...

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Accelerated Life Test and Data Analysis of the Silver Through Hole Printed Wiring Board (가속수명시험을 이용한 은도통홀 인쇄회로기판의 신뢰성연구)

  • 전영호;권이장
    • Journal of Korean Society for Quality Management
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    • v.25 no.2
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    • pp.15-27
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    • 1997
  • This paper describes a highly accelerated life test (HALT, USPCBT) method for rapid qualification testing of STH PWB(Silver Through Hole Printed Wiring Boards). This method was carried out to be an alternative to the present time-consuming standard 1344 hours life testing(THB). The accelerated life test conditions were $121^{\circ}C$/95%R.H. at 50V bias and without bias. Their results are compared with those observed in the standard 1344 hours life test at $40^{\circ}C$/95%R.H. at 50V bias and without bias. The studies were focused on the samples time-to-failure as well as the associated conduction and failure mechanisms. The abrupt drop of insulation resistance is due to the absorption of water vapour. And the continuous drop of insulation resistance is due to the Ag migration. The ratios of time-to-failure of HALT(USPCBT) to THB were 25 and 11 at 50V bias and without bias respectively.

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Patent Survey on Build-up PCB (Build-up PCB 특허출원동향)

  • Yeo Woon Dong;Kim Kang Hoe;Kim Jae Woo;Bae Sang Jin
    • Proceedings of the IEEK Conference
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    • 2004.06a
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    • pp.269-272
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    • 2004
  • Printed circuit boards (PCB) replaced conventional wiring in most electronic equipment I, reducing the size and weight of electronic equipment while improving reliability, uniformity, precision and performance. PCB is used in all kinds of electronic products because they can be mass-produced with very high circuit density and also enable easier trouble-shooting. This paper presents the analyses of the patent information of Build-up PCB which is seen as the most promising solution, as its substrate supports multi-level packaging, thinner board profiles and smaller pitches.

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CSP + HDI : MCM!

  • Bauer, Charles-E.
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.35-40
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    • 2000
  • MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

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Development of the Insufflator for Endoscopic Surgery using the Fluidic System in Printed Circuit Board (유공압 부품이 내장된 인쇄회로기판을 활용한 내시경 수술용 기복기의 개발)

  • Lee, Hee-Nam;Kim, In-Young;Chee, Young-Joon
    • Journal of Biomedical Engineering Research
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    • v.32 no.1
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    • pp.32-36
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    • 2011
  • The insufflators in endoscopic surgery supply carbon dioxide to make the air-filled cavity in the abdomen. It contains many kinds of pneumatic and electronic parts and they are connected with the air tubes and electrical wires. The printed circuit boards (PCB) perform wiring, holding and cooling tasks in electronic systems. In this study, the PCB is used as the air channel for insufflators to decrease the cost, volume, and the malfunction according to aging of the device. Three layers of PCB made of FR4 are combined with prepreg as adhesive which has the internal airway channel according to the design. By mounting the pressure sensors and valves, the PCB based fluidic system is implemented. After calibration of flow sensor, the flow rate of the gas also can be measured. The climate test, temperature test, and biocompatibility test showed this idea can be used in insufflators for laparoscopic surgery.

Three Color Algorithm for Two-Layer Printed Circuit Boards Layout with Minimum Via

  • Lee, Sang-Un
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.3
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    • pp.1-8
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    • 2016
  • The printed circuit board (PCB) can be used only 2 layers of front and back. Therefore, the wiring line segments are located in 2 layers without crossing each other. In this case, the line segment can be appear in both layers and this line segment is to resolve the crossing problem go through the via. The via minimization problem (VMP) has minimum number of via in layout design problem. The VMP is classified by NP-complete because of the polynomial time algorithm to solve the optimal solution has been unknown yet. This paper suggests polynomial time algorithm that can be solve the optimal solution of VMP. This algorithm transforms n-line segments into vertices, and p-crossing into edges of a graph. Then this graph is partitioned into 3-coloring sets of each vertex in each set independent each other. For 3-coloring sets $C_i$, (i=1,2,3), the $C_1$ is assigned to front F, $C_2$ is back B, and $C_3$ is B-F and connected with via. For the various experimental data, though this algorithm can be require O(np) polynomial time, we obtain the optimal solution for all of data.

The characteristics of bismuth magnesium niobate multi layers deposited by sputtering at room temperature for appling to embedded capacitor (임베디드 커패시터로의 응용을 위해 상온에서 RF 스퍼터링법에 의한 증착된 bismuth magnesium niobate 다층 박막의 특성평가)

  • Ahn, Jun-Ku;Cho, Hyun-Jin;Ryu, Taek-Hee;Park, Kyung-Woo;Cuong, Nguyen Duy;Hur, Sung-Gi;Seong, Nak-Jin;Yoon, Soon-Gil
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.62-62
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    • 2008
  • As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.

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