• 자원리싸이클링
• /
• 제11권1호
• /
• pp.9-18
• /
• 2002

폐 컴퓨터 기판(Printed Wiring Boards, PWBs)은 다양한 종류의 금속 및 합금류, 각종의 유기 및 무기화합물 등으로 구성되어 있다. 따라서 폐 기판에 포함된 유가물을 경제적인 방법으로 분리 회수하면 2차 자원으로써 활용가치가 매우 클 것으로 판단되어, 물리적인 선별기술에 의하여 유가금속을 분리 회수하는 데에 따른 특성 연구를 행하였다. 본 연구에는 폐 컴퓨터 기판에 탑재된 소켓류와 칩류를 탈리한 다음 소켓류, 칩류 및 보드류로 분리하여 각각의 산출물의 특성에 따른 적절한 물리적 분리선별 기술을 적용하였다. 소켓류를 파쇄하여 입자크기를 -2.36 mm/+1.18 mm 범위로 조절한 다음 건식 자력선별을 실시하였을 때, 자성산물의 약 97 wt%가 금속류였다. 칩류의 경우에는 -2.36 mm1+0.15 nun의 크기로 분쇄하고 공기분급 및 건 식 자력선별을 행하여 Fe-Ni 97%, Cu 95%를 각각 회수할 수 있었다. 보드류의 경우에는 금속류가 얇게 프린트 된 상태이기 때문에 가능한 단체분리 효과를 향상시키기 위하여 ball mill로 분쇄하였으며, 공기 분급기에 의한 정밀 분급을 행하여 Cu 77%를 회수할 수 있었다.

• 한국표면공학회지
• /
• 제32권3호
• /
• pp.289-296
• /
• 1999

The integration of the LSI has been greatly improved and the circuit patters on the LSI are becoming finer line and pitch. The high-density electronic packaging technology is improved. In order to realize the high-density packaging technology, the density of the circuit wiring of the printed circuit boards have also been more dense. The build-up process multilayer printed circuit board technology have a lot of vias, possibilities of the finer conductor wirings and have a freedom of capabilities of wiring design. The build-up process printed circuit boards have the wiring rules which are the pattern width: $100-20\mu\textrm{m}$, the via hole diameter: $100-50\mu\textrm{m}$. There three kinds of build-up processes as far materials and hole drilling. In this paper, the recent technology trends of the build-up printed circuit board technologies are described.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2001년도 ICCAS
• /
• pp.104.2-104
• /
• 2001

In the intelligent integrated systems, the delay time must be reduced using highly parallel processors, as well as high throughput performance. In this paper, we propose a new concept for building 3D highly parallel processors using multi-layer printed wiring boards with built-in soldering heater (BISH-PWB). The proposed BISH is realized with the long and narrow cupper wiring pattern on the internal layer in the terminal pattern area. Based on the linearity of the cupper resistance vs. temperature, we can measure the BISH, temperature and its calorific value from the heater voltage and current measurements. If we provide the BISH temperature control systems for each BISH, selective multi-point soldering can be realized with same ...

• 품질경영학회지
• /
• 제25권2호
• /
• pp.15-27
• /
• 1997

This paper describes a highly accelerated life test (HALT, USPCBT) method for rapid qualification testing of STH PWB(Silver Through Hole Printed Wiring Boards). This method was carried out to be an alternative to the present time-consuming standard 1344 hours life testing(THB). The accelerated life test conditions were $121^{\circ}C$/95%R.H. at 50V bias and without bias. Their results are compared with those observed in the standard 1344 hours life test at $40^{\circ}C$/95%R.H. at 50V bias and without bias. The studies were focused on the samples time-to-failure as well as the associated conduction and failure mechanisms. The abrupt drop of insulation resistance is due to the absorption of water vapour. And the continuous drop of insulation resistance is due to the Ag migration. The ratios of time-to-failure of HALT(USPCBT) to THB were 25 and 11 at 50V bias and without bias respectively.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
• /
• pp.269-272
• /
• 2004

Printed circuit boards (PCB) replaced conventional wiring in most electronic equipment I, reducing the size and weight of electronic equipment while improving reliability, uniformity, precision and performance. PCB is used in all kinds of electronic products because they can be mass-produced with very high circuit density and also enable easier trouble-shooting. This paper presents the analyses of the patent information of Build-up PCB which is seen as the most promising solution, as its substrate supports multi-level packaging, thinner board profiles and smaller pitches.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
• /
• pp.35-40
• /
• 2000

MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

• 대한의용생체공학회:의공학회지
• /
• 제32권1호
• /
• pp.32-36
• /
• 2011

The insufflators in endoscopic surgery supply carbon dioxide to make the air-filled cavity in the abdomen. It contains many kinds of pneumatic and electronic parts and they are connected with the air tubes and electrical wires. The printed circuit boards (PCB) perform wiring, holding and cooling tasks in electronic systems. In this study, the PCB is used as the air channel for insufflators to decrease the cost, volume, and the malfunction according to aging of the device. Three layers of PCB made of FR4 are combined with prepreg as adhesive which has the internal airway channel according to the design. By mounting the pressure sensors and valves, the PCB based fluidic system is implemented. After calibration of flow sensor, the flow rate of the gas also can be measured. The climate test, temperature test, and biocompatibility test showed this idea can be used in insufflators for laparoscopic surgery.

• 한국컴퓨터정보학회논문지
• /
• 제21권3호
• /
• pp.1-8
• /
• 2016

The printed circuit board (PCB) can be used only 2 layers of front and back. Therefore, the wiring line segments are located in 2 layers without crossing each other. In this case, the line segment can be appear in both layers and this line segment is to resolve the crossing problem go through the via. The via minimization problem (VMP) has minimum number of via in layout design problem. The VMP is classified by NP-complete because of the polynomial time algorithm to solve the optimal solution has been unknown yet. This paper suggests polynomial time algorithm that can be solve the optimal solution of VMP. This algorithm transforms n-line segments into vertices, and p-crossing into edges of a graph. Then this graph is partitioned into 3-coloring sets of each vertex in each set independent each other. For 3-coloring sets $C_i$, (i=1,2,3), the $C_1$ is assigned to front F, $C_2$ is back B, and $C_3$ is B-F and connected with via. For the various experimental data, though this algorithm can be require O(np) polynomial time, we obtain the optimal solution for all of data.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.62-62
• /
• 2008

As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.