• ETRI Journal
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• v.35 no.4
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• pp.734-737
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• 2013

Nonvolatile ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) memory based on an organic thin-film transistor with inkjet-printed dodecyl-substituted thienylenevinylene-thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of -12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 $cm^2/Vs$, $10^5$, and $10^{-10}$ A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.461-466
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• 2007

There has been a great interest in printing technology as a low cost and mass production method for the application of printed electronics such as printed TFT, solar cell, RFID Tag, printed battery, and so on. In this study, apparatuses of gravure-offset printing are developed for fine line-width/gap printing and examining pattern distortion occurred in gravure-offset printing process. The fine line-width/gap pattern shows that it is possible to make around 20 micro-meter line-width/gap printing patterns. Pattern distortion is modeled, and the amount and shape of the distortion are calculated by using commercial FEM code. The roll-to-roll printing system under development consists of unwinder/rewinder, two printing units, one coating unit, drying units, guiding unit, vision system, and other auxiliary devices. For multi-layer printing, the system is designed to be capable of printing two different materials.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.5
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• pp.23-29
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• 2013

Recent advances in printing technology have increased the productivity of the roll-to-roll (R2R) printing process for printed circuitry. In the R2R printed electronics, characteristics of printed and coated layers are one of the most important issues that determine the functional quality of final products. The slot-die technology can coat a large area with high uniformity using low-viscosity materials; determining the process parameters is important to obtain excellent coating qualities. In this study, a viscocapillary model was used to predict qualities of coated layers and patterns. On the basis of analysis results, a novel meta model was derived using design of experiment methodology to improve accuracy. Sensitivity analysis was performed to define major parameters in R2R slot-die coating process. The coating speed was found to most significantly affect the coated layer thickness and was easily controlled. The performance of the proposed model is verified through experimental studies. Based on the statistical analysis results, R2R slot die process can be optimized to guarantee a desired thickness.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.603-609
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• 2013

In this paper, we describe the analysis of inkjet-printed silver (Ag) patterns on epoxy-coated substrates according to several reliability evaluation test method guidelines for conventional printed circuit boards (PCB). To prepare patterns for the reliability analysis, various regular test patterns were created by Ag inkjet printing on flame retardant 4 (FR4) and polyimide (PI) substrates coated with epoxy for each test method. We coated the substrates with an epoxy primer layer to control the surface energy during printing of the patterns. The contact angle of the ink to the coated epoxy primer was $69^{\circ}$, and its surface energy was 18.6 $mJ/m^2$. Also, the substrate temperature was set at $70^{\circ}C$. We were able to obtain continuous line patterns by inkjet printing with a droplet spacing of $60{\mu}m$. The reliability evaluation tests included the dielectric withstanding voltage, adhesive strength, thermal shock, pressure cooker, bending, uniformity of line-width and spacing, and high-frequency transmission loss tests.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.490.2-490.2
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• 2014

Since the general solar cells accept sun light at the front side, excluding the electrode area, electrons move from the emitter to the front electrode and start to collect at the grid edge. Thus the edge of gridline can be important for electrical properties of screen-printed silicon solar cells. In this study, the improvement of electrical properties in screen-printed crystalline silicon solar cells by contact treatment of grid edge was investigated. The samples with $60{\Omega}/{\square}$ and $70{\Omega}/{\square}$ emitter were prepared. After front side of samples was deposited by SiNx commercial Ag paste and Al paste were printed at front side and rear side respectively. Each sample was co-fired between $670^{\circ}C$ and $780^{\circ}C$ in the rapid thermal processing (RTP). After the firing process, the cells were dipped in 2.5% hydrofluoric acid (HF) at room temperature for various times under 60 seconds and then rinsed in deionized water. (This is called "contact treatment") After dipping in HF for a certain period, the samples from each firing condition were compared by measurement. Cell performances were measured by Suns-Voc, solar simulator, the transfer length method and a field emission scanning electron microscope. According to HF treatment, once the thin glass layer at the grid edge was etched, the current transport was changed from tunneling via Ag colloids in the glass layer to direct transport via Ag colloids between the Ag bulk and the emitter. Thus, the transfer length as well as the specific contact resistance decreased. For more details a model of the current path was proposed to explain the effect of HF treatment at the edge of the Ag grid. It is expected that HF treatment may help to improve the contact of high sheet-resistance emitter as well as the contact of a high specific contact resistance.

• Korean Journal of Materials Research
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• v.25 no.12
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• pp.719-726
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• 2015

For a decade, solution-processed functional materials and various printing technologies have attracted increasingly the significant interest in realizing low-cost flexible electronics. In this study, Cu nanoparticles are synthesized via the chemical reduction of Cu ions under inert atmosphere. To prevent interparticle agglomeration and surface oxidation, oleic acid is incorporated as a surface capping molecule and hydrazine is used as a reducing agent. To endow water-compatibility, the surface of synthesized Cu nanoparticles is modified by a mixture of carboxyl-terminated anionic polyelectrolyte and polyoxylethylene oleylamine ether. For reducing the surface tension and the evaporation rate of aqueous Cu nanoparticle inks, the solvent composition of Cu nanoparticle ink is designed as DI water:2-methoxy ethanol:glycerol:ethylene glycol = 50:20:5:25 wt%. The effects of poly(styrene-co-maleic acid) as an adhesion promoter(AP) on rheology of aqueous Cu nanoparticle inks and adhesion of Cu pattern printed on polyimid films are investigated. The 40 wt% aqueous Cu nanoparticle inks with 0.5 wt% of Poly(styrene-co-maleic acid) show the "Newtonian flow" and has a low viscosity under $10mPa{\cdots}S$, which is applicable to inkjet printing. The Cu patterns with a linewidth of $50{\sim}60{\mu}m$ are successfully fabricated. With the addition of Poly(styrene-co-maleic acid), the adhesion of printed Cu patterns on polyimid films is superior to those of patterns prepared from Poly(styrene-co-maleic acid)-free inks. The resistivities of Cu films are measured to be $10{\sim}15{\mu}{\Omega}{\cdot}cm$ at annealing temperature of $300^{\circ}C$.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.750-760
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• 2002

In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn-3.8Ag-0.7Cu were screen printed on both electroless Ni/Au and OSP metal finished micro-via PCBs (Printed Circuit Boards). The interfacial reaction between PCB metal pad finish materials and solder materials, and its effects on the solder bump joint mechanical reliability were investigated. The lead free solders formed a large amount of intermetallic compounds (IMC) than Sn-37Pb on both electroless Ni/Au and OSP (Organic Solderabilty Preservatives) finished PCBs during solder reflows because of the higher Sn content and higher reflow temperature. For OSP finish, scallop-like $Cu_{6}$ /$Sn_{5}$ and planar $Cu_3$Sn intermetallic compounds (IMC) were formed, and fracture occurred 100% within the solder regardless of reflow numbers and solder materials. Bump shear strength of lead free solders showed higher value than that of Sn-37Pb solder, because lead free solders are usually harder than eutectic Sn-37Pb solder. For Ni/Au finish, polygonal shaped $Ni_3$$Sn_4$ IMC and P-rich Ni layer were formed, and a brittle fracture at the Ni-Sn IMC layer or the interface between Ni-Sn intermetallic and P-rich Ni layer was observed after several reflows. Therefore, bump shear strength values of the Ni/Au finish are relatively lower than those of OSP finish. Especially, spalled IMCs at Sn-3.5Ag interface was observed after several reflow times. And, for the Sn-3.8Ag-0.7Cu solder case, the ternary Sn-Ni-Cu IMCs were observed. As a result, it was found that OSP finished PCB was a better choice for solders on PCB in terms of flip chip mechanical reliability.

• Journal of Welding and Joining
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• v.13 no.2
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• pp.82-95
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• 1995

This paper discusses distribution of thermal stress, strain at near the joint and investigates the reliability of solder joints of electronic devices on a printed circuit board. As Electronic devices are composed of different materials, thermal stresses generate at near the interface, such as solder joints and interface between lC device and lead frame pad due to the differences of thermal expansion coefficients, As results of thermal stress, strain, micro crack often occurs thermal fatigue fracture at the interface of different materials, The initiation and propagation of micro crack depend on the environmental conditions, such as storage temperature and thermal cycling. Finally, this paper experimentally shows a way to suppress micro cracks by using Fe-Ni alloy clad lead frame, and investigates crack and thermal fatigue fracture of TSOP(Thin small outline package) type on printed circuit board.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.18.1-18.1
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• 2010

Here, we introduce our R&D status and strategies for printed electronics containing the two types of aspects such as materials and process/architectures. Specially, in this talk, we focus on the high-performance polymer thin film transistors (PTFTs) backplanes fabricated by ink-jet printing using new polymer semiconductors for the applications of flexible display.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.426-426
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• 2007

We report the field emission characteristics of transparent single-walled carbon nanotube (SWNT) film printed using an inkjet. Pure SWNTs dispersed in dimethylformamide were printed in a transparent layer on indium-tin oxide-coated glass and annealed at $350^{\circ}C$. After taping treatment, SWNTs were oriented vertically on the substrate. The front and the back of the fabricated device produced simultaneous emissions of identical quality. In addition, inkjet printing directly achieved a patterned emission, without a secondary pattern process. This method allows simple fabrication using only SWNTs, without the use of other additives.