• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.160-160
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• 2008

In practical etching process, etch ant is sprayed on the metal-deposited panel through nozzles collectively connected to the manifold and that panel is usually composed of many PCB(printed circuit board)'s. The etching uniformity, the difference between individual PCB's on the same panel, has become one of most important features of etching process. In this paper, the prediction of nozzle trajectory has been performed by the combination of algebraic formula and numerical simulation. With the pre-determined geometrical factors of nozzle distribution, the trajectories of individual nozzles were predicted with the change of process operational factors such as panel speed, nozzle swing frequency and so on. As results, two dimensional distribution of impulsive force of etchant spray which could be considered as a key factor determining the etching performance have been successfully obtained. Though only qualitative prediction of etching uniformity have been predicted by the process developed in this study, the expansion to the quantitative prediction of etching uniformity is expected to be apparent by this study.

• 한국표면공학회지
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• 제46권4호
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• pp.153-157
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• 2013

The defect like the void or seam is frequently generated in the PCB (Printed Circuit Board) Via-Filling plating inside via hole. The organic additives including the accelerating agent, inhibitor, leveler, and etc. are needed for the copper Via-Filling plating without this defect for the plating bath. However, the decomposition of the organic additive reduces the lifetime of the plating bath during the plating process, or it becomes the factor reducing the reliability of the Via-Filling. In this paper, the interaction of each organic additives and the decomposition of additive were discussed. As to the accelerating agent, the bis (3-sulfopropyl) disulfide (SPS) and leveler the Janus Green B (JGB) and inhibitor used the polyethlylene glycol 8000 (PEG). The research on the interaction of the organic additives and decomposition implemented in the galvanostat method. The additive decomposition time was confirmed in the plating process from 0 Ah/l (AmpereHour/ liter) to 100 Ah/l with the potential change.

• 한국산학기술학회논문지
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• 제13권5호
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• pp.2015-2022
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• 2012

본 논문은 항공전자장비의 구조해석을 통한 하우징과 인쇄회로기판의 해석과 설계에 관한 것으로 대기자료 컴퓨터 개발 사례를 통한 연구결과이다. 항공기에 장착되는 전자장비는 전기적인 특성 외에도 운용환경에 따른 구조 설계가 매우 중요하고 설계 단계에서부터 해석을 통한 입증이 되어야 한다. 본 연구에서는 장착되는 항공 장비의 응력과 진동 요구도를 분석하여 해석 결과를 통하여 설계에 적용하고 요구도에 대해서 입증하는 방법에 대한 것이다. 구조 해석은 상용 소프트웨어를 사용하였으며 하우징의 내부 리브 설계에 대한 적합성을 확인하고 인쇄회로 기판의 변위를 계산하여 전자 부품 배치에 활용하는 방법에 대해서 제시하였다.

• 한국전자파학회논문지
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• 제12권4호
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• pp.494-502
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• 2001

GPS(Global Positiong System)와 GLONASS(GLObal NAvigation Satellite System) 는 위치와 시각을 제공하는 기초 기술이며 항법 분야, 측지분야, 자세 측정 및 제어 분야 등 그 응용분야가 다양하다. 그러나 GPS나 GLONASS는 각기 제한된 가시 위성의 수로 인해 정확한 항법 해를 얻는데 어려움이 있으며, 또한 하나의 항법 시스템만을 이용하는 경우 의존도가 너무 높아지게 되어 전략적인 측면에서도 불리하다. 이러한 측면에서 GPS와 GLONASS 의 통합수신은 보다 정확한 항법 해를 구할 수 있고 보다 나은 시스템의 안정도를 가져올 수 있다. 이를 목적으로 GPS/GLONSS 통합 수신용 RF 전단부를 130$\times$80 mm$^2$의 PCB상에 구현하였고 실제 시스템에 적용 가능한지를 측정하였으며 GLONASS 수신기의 one chip화의 가능성을 검토하였다.

• 전력전자학회논문지
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• 제20권6호
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• 한국자동차공학회논문집
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• 제6권5호
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• pp.153-161
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• 1998

The knock in a spark ignition engine has been investigated to avoid the damage to the engine and unpleasant feeling caused by the pressure waves propagating across the combustion chamber. Knock intensity and knock onset angle were used as physical parameters to quantify the knock characteristics. The knock intensity is defined as a peak to peak value of the bank pass filtered combustion pressure signal and the knock onset angle is determined as the crank angle at which this signal exceeded the threshold level on each cycle. The cyclic variation of knock in four valve single cylinder engine was investigated with these two parameters. The location of autoignition was also examined by ion probes in the cylinder head gasket and squish region in the combustion chamber. For this measurement, a single cylinder engine was modified to accept the pressure transducer, 18 ion probes in the squish region and 8 ion probes in the specially designed PCB (Printed \ulcornerCircuit Board) cylinder head gasket.

• 제어로봇시스템학회논문지
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• 제6권2호
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• 한국전기전자재료학회논문지
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• 제22권7호
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• pp.572-575
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• 2009

In this study, we proposed WLED(White-Light Emitting Diode) driver IC for mobile applications. This IC drove WLED for mobile applications with low input voltage and high efficiency by using boost converter. The device was designed by using boost converter applied current-mode control algorithm and provided PWM(Pulse Width Modulation) & analog dimming. Designed IC consisted of bias block, drive block, control block, protection block. We confirmed this device worked well through a application PCB (Printed Circuit Board) test.

• 대한산업공학회지
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• 제39권1호
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• pp.10-19
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• 2013

Dispatching rule plays an important role in a hybrid flow shop. Finding the appropriate dispatching rule becomes more challenging when there are multiple criteria, uncertain demands, and dynamic manufacturing environment. Using a single dispatching rule for the whole shop or a set of rules based on a single criterion is not sufficient. Therefore, a multi-criteria decision making technique using 'the order preference by similarity to ideal solution' (TOPSIS) and 'analytic hierarchy process' (AHP) is presented. The proposed technique is aimed to find the most suitable set of dispatching rules under different manufacturing scenarios. A simulation based case study on a PCB manufacturing process is presented to illustrate the procedure and effectiveness of the proposed methodology.

• 산업공학
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• 제11권3호
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• pp.1-13
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• 1998

This paper addresses a scheduling scheme for Flexible Flow Shop(FFS) in the case that a factory is a sub-plant of an electronic device manufacturing plant. Under this environment, job orders for the sub-plants in the production route are generated together with job processing time bucket when the customer places orders for final product. The processing time bucket for each job is a duration from possible release date to permissible due date. A sub-plant modeled FFS should schedule these jobs orders within time bucket. Viewing a Printed Circuit Board(PCB) assembly line as a FFS, the developed scheme schedules an incoming order along with the orders already placed on the scheduled. The scheme consists of the four steps, 1)assigning operation release date and due date to each work cells in the FFS, 2)job grouping, 3)dispatching and 4)machine allocation. Since the FFS scheduling problem is NP-complete, the logics used are heuristic. Using a real case, we tested the scheme and compared it with the John's algorithm and other dispatching rules.