• 전기학회논문지
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• 제63권7호
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• pp.1013-1018
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• 2014

This paper described the development of equalizing spacer for minimization of voltage drop according to DC feeder extension. Power consumption is increased as shorter interval of train driving time and transportation capacity increase in urban subway. Therefore we investigated voltage drop of catenary at a point in case of traction driving of a train in parallel to the DC power supply system. Based on it's result, equalizing spacer is designed and fabrication to minimize the voltage drop in accordance with the power supply line arranged in three rows, and then its performance was confirmed that the stress distribution of main body and the distributed load are satisfied through the body structure modeling.

• Journal of Power Electronics
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• 제14권2호
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• pp.351-361
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• 2014

The discrete torque generation mechanism and inherently nonlinear magnetic characterization of switched reluctance motors lead to unacceptable torque ripples and limit the application of these motors. In this study, a phase current profiling technique and torque sharing function are proposed in consideration of magnetic saturation effects and by minimizing power loss in the commutation area between the adjacent phases. Constant torque trajectories are considered in incoming and outgoing phase current planes based on nonlinear T-i-theta curves obtained from experimental measurements. Optimum points on constant torque trajectories are selected by improving drive efficiency and minimizing copper loss in each rotor position. A novel analytic invertible function is introduced to express phase torque based on rotor position and its corresponding phase current. The optimization problem is solved by the proposed torque function, and optimum torque sharing functions are derived. A modification method is also introduced to enhance the torque ripple-free region based on simple logic rules. Compared with conventional torque sharing functions, the resultant reference current from the proposed method has less peak and effective values and exhibits lower copper loss. Experimental and simulation results from a four-phase 4 KW 8/6 SRM validate the effectiveness of the proposed method.

• 한국자동차공학회논문집
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• 제5권1호
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• pp.216-216
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• 1997

We developed the durability estimation and design systems to minimize the volume, considering the durability, efficiency, and design requirements of worm gears. That is, we consider each kind of factors affecting on durability on the basis of AGMA Standard for the cylindrical and double-enveloping worm gears. We also estimate input power on the basis of wear and durability, bending strength and deflection of worm shaft, and we developed the durability estimation and design systems of power transmission worm gears introducing the optimal design method on the personal computer to be easily used in field. Also, we developed a method which converts the design variables obtained from the optimal design method to integer values(number of worm threads, number of worm threads, number of worm wheel teeth, etc.,) to be used in real design and production. The developed durability estimation and design method can be easily applied to the design of worm gears used as power transmission devices in machineries and is expected to be used for weight minimization of worm gear unit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 D
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• pp.1838-1839
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• 2006

In this paper, a loss-minimization nonlinear torque control for Electrical Vehicle(EV) induction motors is proposed. To improve the efficiency of the induction motors, it is important to find the optimal flux reference that minimize power losses. The proposed optimal flux reference is derived using a power loss function that is constructed with stator resistance losses, rotor resistance losses and core losses. And the time-varying load torque and the rotor resistance variation are considered in the power loss function. An algorithm that identifying the load torque is used. The rotor flux observer is used to obtain an accurate flux value regardless of the rotor resistance variation. Simulation results show a significant reduction in energy losses.

• ETRI Journal
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• 제6권4호
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• pp.31-36
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• 1984

This paper presents an efficient method for real power loss minimization and for improvements in voltage profiles. This method is accomplished by optimal control of reactive power in the system. The problem is formulated as an optimization problem, suitable for solution by linear programming technique. After establishing the objective function for minimizing the system losses with the help of linearised sensitivity relationships of control variables, i. e., the transformer tap position, generator terminal voltages and switchable reactive power sources. The linear programming technique is used to determine the optimal adjustments to the above variables, simultaneously satisfying the constraints. The proposed algorithm has been tested on a sample system and the result is presented and discussed.

• 한국정보과학회논문지:시스템및이론
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• 제30권9호
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• pp.504-511
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• 2003

논리회로 합성에서 함수의 대칭성을 이용하여 면적이나 시간 지연을 최소화하는 문제는 많은 시간동안 연구되어 왔다. 본 논문은 최근 들어 면적이나 시간지연 보다도 더 중요하게 여겨지는 전력 소모를 최소화하는데, 회로 대칭성이 어떻게 이용되는 지에 대한 연구를 소개한다. 이 논문에서 회로의 대칭성에 대한 폭넓은 정의를 소개하고, 각 대칭성간의 관계에 대해 논의하며, 각 회로의 대칭성이 어떻게 전력을 줄이는데 유용할 수 있는지에 대해 논의한다. 또한, 회로에 존재하는 주 입력(primary input)과 내부 노드사이에 존재하는 대칭성을 찾아내는 알고리즘을 소개한다. 이 논문에서 소개하는 알고리즘의 특징은 첫째, 면적이나 속도지연의 증가가 거의 없이, 전력 소모를 줄여주는 효과적인 재합성 기법이란 것이다. 둘째, 대부분의 다른 휴리스틱(heuristic) 알고리즘과는 달리, 회로의 스위칭 (switching) 양에 있어 단조 향상(monotonic improvement)을 보장한다. 이미 잘 알려진 바와 같이 CMOS 회로에서는 스위칭 양이 전력소모에 대부분을 차지하므로, 알고리즘의 적용 후에 회로가 전력 소모 면에서 계속적인 향상을 이룰 수 있게 한다는 점에서 매우 효과적이라 하겠다. 알고리즘의 효과를 검증하기 위해서, MCNC 벤치마크 회로를 이용하여 실험을 시행하였고, 실험 결과, 속도나 면적에 대한 오버헤드가 거의 없으면서 평균 12%의 전력 소모를 줄일 수 있었다.

• 전력전자학회논문지
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• 제24권3호
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.231-233
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• 2005

For the low-power design of the mobile multimedia system architecture, this paper modeling the mobile multimedia system and analysis the power consumption profile about the whole communication environment. The mobile system model consist of air interface, RIP front-end, base-band processing module and human interface. For the result of power consumption profile analysis, the power consumption of multimedia processing is above 60% compare to the whole power consumption in mobile multimedia system. To minimize the power consumption in processing module which consumes the large power, this paper proposed the Microscopic DVS technique which applies the optimum voltage for the each multimedia frame. For the simulation result, proposed power minimization technique reduce the power consumption about 30%.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1329-1339
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• 2017

This paper presents the power scheduling of a multi-microgrid (MMG) system using an optimization technique called particle swarm optimization (PSO). The PSO technique has been shown to be most effective at solving the various problems of the economic dispatch (ED) in a power system. In addition, a new MMG system configuration is proposed in this paper, through which the optimal power flow is achieved. Both optimization and power trading methods within an MMG are studied. The results of implementing PSO in an MMG system for optimal power flow and cost minimization are obtained and compared with another attractive and efficient optimization technique called the genetic algorithm (GA). The comparison between these two effective methods provides very competitive results, and their operating costs also appear to be comparable. Finally, in this study, power scheduling and a power trading method are obtained using the MATLAB program.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.