• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.334-336
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• 2005

This paper proposes a simple MPPT control scheme of a Current- Control-Loop Error system Based that can be obtains a lot of advantage to compare with another digital control method, P&O and IncCond algorithm, that is applied mostly a PV system. An existent method is needed an expensive processor such as DSP that calculated to change the measure power of a using current and voltage sensor at the once. But, a proposed method is easy to solve the cost reduction and power unbalance problems that it is used by control scheme to limit error of a current control of common sensor. This proposed algorithm had verified through a simulation and an experiment on battery charger using PIC that is the microprocessor of a low price.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1477-1485
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• 2019

This paper proposes an effective model predictive current control (MPCC) that involves using 10 virtual voltage vectors to reduce the current harmonics and common-mode voltage (CMV) for a two-level five-phase voltage source inverter (VSI). In the proposed scheme, 10 virtual voltage vectors are included to reduce the CMV and low-order current harmonics. These virtual voltage vectors are employed as the input control set for the MPCC. Among the 10 virtual voltage vectors, two are applied throughout the whole sampling period to reduce current ripples. The two selected virtual voltage vectors are based on location information of the reference voltage vector, and their duration times are calculated using a simple algorithm. This significantly reduces the computational burden. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.417-424
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• 2022

This study proposes a current-balancing technique for an interleaved buck converter using a variable inductor and a snubber capacitor. The proposed scheme balances the inductor current by using the variable inductor and enables zero voltage switching under all load ranges. With the variable inductor, the ripple of inductor current changes according to load variation. In addition, a 1.6 kW prototype is built to verify the validity of the proposed scheme, and the experimental results are successfully obtained.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.511-517
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• 2006

The key issues in high power, high energy applications such as electromagnetic launchers include safety, reliability, flexibility, efficiency, compactness, and cost. To explore some of the issues, a control scheme for a large current wave-forming was designed, built and experimentally verified using a 2.4MJ pulse power system (PPS). The PPS was made up of eight capacitors bank unit, each containing six capacitors connected in parallel. Therefore there were 48 capacitors in total, with ratings of 22kV and 50kJ each. Each unit is charged through a charging switch that is operated by air pressure. For discharging each unit has a triggered vacuum switch (TVS) with ratings of 200kA and 250kV. Hence, flexibility of a large current wave-forming can be obtained by controlling the charging voltage and the discharging times. The whole control system includes a personal computer(PC), RS232 and RS485 pseudo converter, electric/optical signal converters and eight 80C196KC micro-controller based capacitor-bank module(CBM) controllers. Hence, the PC based controller can set the capacitor charging voltages and the TVS trigger timings of each CBM controller for the current wave-forming. It also monitors and records the system status data. We illustrated that our control scheme was able to generate the large current pulse flexibly and safely by experiments. The our control scheme minimize the use of optical cables without reducing EMI noise immunity and reliability, this is resulting in cost reduction. Also, the reliability was increased by isolating ground doubly, it reduced drastically the interference of the large voltage pulse induced by the large current pulse. This paper contains the complete control scheme and details of each subsystem unit.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.58-64
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• 2004

This paper proposes a novel control scheme for the harmonic reduction of DC power regenerating systems, which can regenerate the excessive DC power from DC bus line to AC supply in subway systems. In the developed regenerating systems controlled by MAC(Modified a-Conduction) method, the order of remaining harmonics are 12k$\pm$1. In SHE(Selected Harmonic Elimination) method proposed in this paper, however, the l1th and 13th harmonics are additionally eliminated. And moreover 23rd harmonics, lowest order harmonics among the remaining harmonics, is eliminated by 23rd AC filter furnished at the output terminals of regenerating systems. To verify the validity of the proposed SHE-based harmonic reduction technique, computer simulations are carried out. Simulation results show that the THDs of output voltages are lower than that of the MAC method and the THDs in the control range are in the range of 0.53-0.68 percents.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.200-220
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• 2016

Orthogonal frequency division multiplexing (OFDM) signals suffer from the problem of large peak-to-average power ratio (PAPR) which complicates the design of the analog front-end of the system. Companding is a well-known PAPR reduction technique that reduces the PAPR by transforming the signal amplitude using a deterministic function. In this paper, a novel piecewise linear companding transform is proposed. The design criteria for the proposed transform is developed by investigating the relationships between the compander and decompander's profile and parameters with the system's performance metrics. Using analysis and simulations, we relate the companding parameters with the bit error rate (BER), out-of-band interference (OBI), amount of companding noise, computational complexity and average power. Based on a set of criteria developed thereof, we formulate the design of the proposed transform. The main aim is to preserve the signal's attributes as much as possible for a predetermined amount of PAPR reduction. Simulations are carried out to evaluate and compare the proposed scheme with the existing companding transforms to demonstrate the enhancement in PAPR, BER and OBI performances.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1042-1050
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• 2005

This paper proposed a novel low-power video decoding scheme for mobile multimedia communication. In general, there are quite a large number of non-coded blocks in the encoded bitstream where all quantized DCT coefficients are truncated into zero. When the number of the non-coded blocks are known at the start of frame decoding, the amount of computation reduction can be precisely estimated for frame decoding. When the computation reduces, the operation speed and the corresponding supply voltage of VLSI circuits in the decoder also reduce, thus thus power consumption also reduces. In the proposed scheme, the number of the non-coded blocks is stored in the frame header of the encoded bitstream, and the decoder efficiently reduces the power consumption exploiting this information. Simulation results show that the proposed scheme reduces the power consumption to about 1/20.

• Korean Journal of Computational Design and Engineering
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• v.17 no.5
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• pp.312-323
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• 2012

Planetary gearing is a gear system consisting of one or more planet gears, revolving about a sun gear. While the planetary gear system has many advantages- for example, high power density, large reduction in a small volume, multiple kinematic combinations, pure torsional reactions, and coaxial shafting, it has not been widely used because of its high bearing loads, inaccessibility, and design complexity. It is also necessary to shift several pairs of gear profiles at a same time. Therefore, designing profile shifted planetary gear system is a difficult and know-how dependent job. This study provides a practical solution to design a profile shifted gear system by the procedural design scheme, and proposes a bearing integrated structure of the dual stage profile shifted gear system with a robust output end. A dual stage profile shifted gear system with the bearing integrated structure is manufactured by the proposed design scheme in this study. This gear system is verified that it is good enough to commercialize, because it has high performance with high gear ratio and robust output end against axial and radial directional runouts in a small space.