• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.20 no.1
• /
• pp.41-47
• /
• 2006

This paper presents harmonic evaluation of an IAT(Intra Airport Transit) system in Incheon International Airport. It will be used for electric vehicles with 80[kW] per car produced by Mitsubishi Heavy Industries Ltd, and which is constructed with SIV(Static Inverter), VVVF controller and two induction motor. The vehicles operated in the IAT system can be treated as rapidly changing DC loat and at a feeding substation, 3-phase electric power is transferred to DC 750[V] by rectifier. Since vehicles are changing continuously, the voltages for the load fluctuate in the IAT system, and moreover, the voltage fluctuation generates high-order harmonics. It results the difficulty in maintaining power quality in KEPCO systems' side. The power quality of the IAT system in Incheon International Airport is evaluated using PSCAD/EMTDC simulator in the paper. The THD(Total Harmonic Distortion) of voltages and TDD(Total Demand Distortion) of currents, indices are calculated for the IAT system using the results of PSCAD/EMTDC dynamic simulation.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.10 no.5
• /
• pp.508-517
• /
• 2005

This paper describes a high performance voltage controller for 3-phase 4-wire UPS (Uninterruptible Power Supply) system, and proposes a new scheme of synchronous reference frame controller in order to compensate for the voltage distortions due to unbalanced and nonlinear loads. Proposed scheme can eliminate the negative sequence voltage component due to unbalanced loads and also reduce the harmonic voltage component due to non-linear loads, even when the bandwidth of voltage control loop is a very low. In order to compensate for the effects of unbalanced loads, the synchronous reference frame controller with the positive and negative sequence computation block is proposed, and the synchronous frame controller with a bandpass filter is proposed to compensate for the selected harmonic frequency of output voltage. The effectiveness of the proposed scheme has been investigated and verified through computer simulations and experiments by a 30kVA UPS.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.2
• /
• pp.160-167
• /
• 2009

To detect islanding mode when the grid is being tripped is a major safety issue in the Utility Interactive Photo Voltaic (UIPV) system. In this paper, analytical design method is suggested for AFD & RPV method under IEEE 929-2000 recommended islanding test condition. We have discussed that there is a same point. we injected reactive component of the current by AFD & RPV methods, but the current reference generated is other waveform. Possible if amount of reactive components in this methods are same each method, there is happened same rates frequency variation. To verify the validity of the analytical comparison, this paper presents simulation and experimental results from single phase, 3[kW] inverter for the transformerless UIPV system.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.10
• /
• pp.124-129
• /
• 1990

This paper describes a new method to eliminate some selected harmonics (5,7,11) in PWM waveforms using Walsh and related orthogonal functions. Previous analyses of PWM waveforms are based on the nonlinear equations requiring iterative solution methods which are not practical in real-time systems. In addition, synthesis of low harmonics waveform at high power system is not easy to implement with power electronic hardware. The goal of this paper is to achieve the harmonics elimination in a PWM waveform by replacing the nonlinear equations in Fourier analysis with linear algebraic equations resulting from the use of orthogonal Walsh equation. This paper also describes how to synthesize low ordered harmonic waveforms with practical power electronic hardware. Walsh and Radmacher functions are easily manipulated by Harmuth's array generator, and those algorithms are accurate, computationally efficient and faster than algorithm based on Fourier analysis. In addition, this method is simulated to synthesize periodic PWM waveforms. From the experi-mental results, it is shown that single-phase PWM waveform are identified with the proposed method. And these methods are also extended to three-phase PWM waveforms in this paper.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.3
• /
• pp.154-161
• /
• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.4
• /
• pp.652-658
• /
• 2006

This paper deals with an electronic ballast for hish intensity short-arc discharge lamps, which consists of a boost converter, a step down converter operated as a current source with power regulation and a low frequency inverter with external ignition circuit The ignition circuit generates high voltage pulses of 130[Hz] up to 5 [kV]. A reignition circuit is equipped in the ballast, and it operates the lamp at a regular interval for protection when an ignition fails. Acoustic resonance phenomenon was eliminated by operating a low frequency square wave voltage and current. The measured lamp voltage, current and consumption power were 123.8 [V], 8.1 [A] and 1,002 [W], respectively. From the experiment, we confirmed that the prototype ballast operates the lamp with a constant power.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2450-2456
• /
• 2015

In this paper, we propose a real-time remote monitoring system for distributed solar power generation system. The proposed system consists of PVC, UTC, OTC and monitoring server. PVC collects the operational information from the PV's inverter via serial interface. The sensing data is transmitted to the server by wireless communications and stored in the DB server. The PV's status is monitored via UTC, and the operating of PVC and UTC are managed by OTC. In addition, by providing information about the power generated by PV system and failure diagnosis in real time, the proposed system shows the possibility of reducing the maintenance costs and improved failure recovery time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.10a
• /
• pp.897-900
• /
• 2007

This paper presents a study on the DSP controller and IGBT inverter driver design for the power-by-wire(PBW) system using BLDC servo motor. This BLDC servo motor system was realized with DSP(Digital Signal Processor) and IGBT inveter module. The PBW system needs speed control of servo motor for linear thrust action. This paper implements a servo controller with vector control and min-max PWM technique. As CPU of controller, TMS320F2812 DSP was adopted because it has PWM(Pulse Width Modulation) waveform generator, A/D(Analog to Digital) converter, SPI( Serial Peripheral Interface) port and many input/output port etc.

• Journal of Power Electronics
• /
• v.18 no.3
• /
• pp.702-713
• /
• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.46-51
• /
• 2002

A new interleaved synchronous mirror delay(SMD) is proposed in order to reduce the circuit size and the power. The conventional interleaved SMD has multiple pairs of forward delay array(FDA) and backward delay away(BDA) in order to reduce the jitter. The proposed interleaved SMD. requires one FDA and one BDA by changing the position of multiplexer. Moreover, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on a 0.25um two-metal CMOS technology.