• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.641-650
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• 2008

As portable devices are used widely, power management algorithm is essential to extend battery use time on small-sized battery power. Although many methods have been proposed, they assumed the voltage transition overhead was negligible or was considered partially. However, the voltage transition overhead might not guarantee to schedule real-time tasks in portable multimedia systems. This paper proposes the adaptive power-aware algorithm to minimize the power consumption by considering the voltage transition overhead. It selects only a few discrete frequencies from the whole frequencies of a system and adjusts the interval between two consecutive frequencies based on the system utilization to reduce the number of frequency change. This algorithm saves the power consumption about 10 to 25 percent compared to a CC RT-DVS method and a frequency-smoothing method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.884-891
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• 2006

A wireless sensor node is typically battery operated and energy constrained. Therefore it is critical to design efficient power management technique and scheduling technique. In this paper, we propose an OS-level power management technique for energy saving of wireless sensor node, it is called EA-SENTAS (Energy-Aware Sensor Node TAsk Scheduling). It can decrease the energy consumption of a wireless sensor node to use task scheduling technique that shut down components or use low power mode of each component when not needed. Simulation results show that EA-SENTAS saves energy up to 56 percent to compare with conventional duty cycle.

• ETRI Journal
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• v.37 no.1
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• pp.118-127
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• 2015

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.1
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• pp.16-22
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• 2016

This paper addresses the load usage scheduling in the HEMS for residential power consumers. The HEMS would lead the residential users to change their power usage, so as to minimize the cost in response to external information such as a time-varying electricity price, the outside temperature. However, there may be a consumer's inconvenience in the change of the power usage. In order to improve this, it is required to understand the pattern of load usage according to the external information. Therefore, this paper suggests a methodology to model the load usage pattern, which classifies home appliances according to external information affecting the load usage and models the usage pattern for each appliance based on a copula function representing the correlation between variables. The modeled pattern would be reflected as a constraint condition for an optimal load usage scheduling problem in HEMS. To explain an application of the methodology, a case study is performed on an electrical water heater (EWH) and an optimal load usage scheduling for EHW is performed based on the branch-and-bound method. From the case study, it is shown that the load usage pattern can contribute to an efficient power consumption.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.55-61
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• 2011

We propose power-saving real-time scheduling method for mixed task sets which consist of both time-based periodic and event-based aperiodic tasks in the automotive operating system. In this system, we have to pursue maximization of power-saving using the slack time estimation and minimization of response time of aperiodic tasks simultaneously. However, since these two goals conflict each other, one has to make a compromise between them according to the given application domain. In this paper, we find the adjustment factor which gives better response time of aperiodic tasks with slight power consumption increase. The adjustment factor denotes the gravity of response time for aperiodic tasks. We apply the ccEDF scheduling for time-based periodic tasks and then calculate new utilization to be applied to the adjustment factor. In this paper, we suggest the lccEDF algorithm to make a tradeoff between the two goals by systematically adjusting the factor. Simulation results show that our approach is excellent for variety of task sets.

• The KIPS Transactions:PartC
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• v.11C no.4
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• pp.555-562
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• 2004

We consider differentiated bandwidth allocation for a piconet in short-range wireless personal network systems : Bluetooth. Since bandwidth requirements nay vary among applications/services, and/or it may change over time, it is important to decide how to allocate limited resources to various service classes to meet their service requirements. We propose a simple and efficient bandwidth allocation mechanism which meets bandwidth requirements of various service types while saving power consumption by a Power saying mode, i.e., sniff node. We compare our proposed mechanism with a conventional (weighted) round-robin polling scheme and show that it achieves significant improvement of hroughput, delay, and power consumption.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Journal of Computing Science and Engineering
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• v.7 no.1
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• pp.30-43
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• 2013

Multicore and multiprocessor systems with dynamic voltage scaling architectures are being used as one of the solutions to satisfy the growing needs of high performance applications with low power constraints. An important aspect that has propelled this solution is effective task/application scheduling and mapping algorithms for multiprocessor systems. This work proposes an energy aware, offline, probability-based unified scheduling and mapping algorithm for multiprocessor systems, to minimize the number of processors used, maximize the utilization of the processors, and optimize the energy consumption of the multiprocessor system. The proposed algorithm is implemented, simulated and evaluated with synthetic task graphs, and compared with classical scheduling algorithms for the number of processors required, utilization of processors, and energy consumed by the processors for execution of the application task graphs.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.151-154
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• 2014

An energy of applications had consumed through the complexed inter-action with operating systems, run-time environments, compiler, and applications on various mobile devices. In these days, challenged researches are studying to reduce of energy consumptions that uses energy-oriented high-level and low-level compiler techniques on mobile devices. In this paper, we intented to reduce an energy consumption of Java mobile applications that applied a list instruction scheduling for energy dissipation from dalvik bytecode which extracted Android dex files. Through this works, we can construct the optimized power and energy environment on mobile devices with the limited power supply.