• Journal of Industrial Technology
• /
• v.30 no.A
• /
• pp.83-88
• /
• 2010

Recently, the LED lighting is widely used to illumination purpose due to its high luminous efficiency and the long life time. However, the light power and lifetime is reduced by junction temperature increment of LED. So it is important to measure the junction temperature accurately. In this paper, we proposed a new design and implementation method of high power LED junction temperature measurement circuit. The proposed circuit has two current sources which are a driving current source and a measurement is verified by experiment, and the result shows that the proposed circuit is appropriate to practical use.

• Journal of Power Electronics
• /
• v.14 no.4
• /
• pp.621-631
• /
• 2014

To invigorate the tapped-inductor boost (TIB) topology in emerging high step-up applications for off-grid products, a lossless snubber consisting of two capacitors and three diodes is proposed. Since the switch voltage stress is minimized in the proposed circuit, it is allowed to use a device with a lower cost, higher efficiency, and higher availability. Moreover, since the leakage inductance is fully utilized, no effort to minimize it is required. This allows for a highly productive and cost-effective design of the tapped-inductor. The proposed circuit also shows a high step-up ratio and provides relaxation of the switching loss and diode reverse-recovery. In this paper, the operation is analyzed in detail, the steady-state equation is derived, and the design considerations are discussed. Some experimental results are provided to confirm the validity of the proposed circuit.

• Proceedings of the KIEE Conference
• /
• 2003.04a
• /
• pp.163-165
• /
• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means o( the decision of the operating system. In this paper, we designed of low power system by using Power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• Journal of Electrical Engineering and Technology
• /
• v.3 no.1
• /
• pp.130-134
• /
• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• Proceedings of the KSR Conference
• /
• 1999.05a
• /
• pp.328-335
• /
• 1999

Three phase full bridge rectifier has been used to obtain dc voltage from three phase ac voltage source. The rectifier system has drawbacks that power factor is low and power flow is unidirectional. Therefore, when dc voltage increases due to regeneration of power the dynamic resister for dissipation of regeneration power must be installed. But three phase PWM converter can be controlled to operate with unity power factor and bidirectional power flow. Therefore when the PWM converter is used as do supply system, the dissipating resistor is not necessary. On this thesis, in order to design a controller having good performance, the hee phase PWM converter is completely modeled by using circuit DQ-transformation and thus a general and simple instructive equivalent circuit is obtained; the inductor set becomes a second order gyrator-coupled system and three phase inverter becomes a transformer as well. Under given phase angle(${\alpha}$) and modulation index(MI) of the three phase inverter, the dc and ac characteristics are obtained by analysis of the transformed equivalent circuit The validity of the equivalent circuit is confirmed through PSPICE simulation. And based on the dc and ac characteristics a controller with unity power factor is proposed.

• Journal of IKEEE
• /
• v.14 no.2
• /
• pp.1-8
• /
• 2010

In this paper, Green Mode Power IC is designed to reduce the standby power. The proposed and designed IC works for the Switch Mode Power Supply(SMPS) and has the function of PWM. To reduce the unnecessary electric power, burst mode and skip mode section are introduced and controlled by external power MOSFET to diminish the standby power. The proposed IC is designed and simulated by KEC 30V-High Voltage 0.5um CMOS Process. The structure of proposed IC is composed of voltage regulator circuit, voltage reference circuit, UVLO(Under Voltage Lock out) circuit, Ibias circuit, green circuit, PWM circuit, OSC circuit, protection circuit, control circuit, and level & driver circuit. Measuring the current consumption of each block from the simulation results, 1.2942 mA of the summing consumption current from each block is calculated and ot proved that it is within the our design target of 1.3 mA. The current consumption of the proposed IC in this paper is less than a half of conventional ICs, and power consumption is reduced to the extent of 1W in standby mode. From the above results, we know that efficiency of proposed IC is superior to the previous IC.

• The KIPS Transactions:PartA
• /
• v.15A no.5
• /
• pp.243-248
• /
• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• IEIE Transactions on Smart Processing and Computing
• /
• v.2 no.4
• /
• pp.248-254
• /
• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.5 no.4
• /
• pp.327-334
• /
• 2000

In this paper, the circuit model using circuit averaging method for full bridge for full bridge converter is suggested. This model can represent the physical characteristics of converter circuits appropriately. At most of high capacity DC-DC converter application parts, full bridge converter is adapted for main circuit of power supply. Design and analysis of full bridge converter is no trouble with circuit model. The validity of circuit model is verified through computer simulation and practical welding experiment of welding machine with full bridge converted model.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2006.05a
• /
• pp.365-366
• /
• 2006

Hydraulic circuit breaker is the most popular type of electric power circuit breaker because of its superiority of operating performance and capacity. For the improvement of hydraulic circuit breaker's operating performance, it is very important to analyze its dynamic behavior characteristics. In this study, hydraulic circuit is modeled, analyzed and experimented. As a result, the experimental data agree well with the numerical ones, and the numerical results can be applied to the design and the improvement of hydraulic electric power circuit breaker.