• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.3
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• pp.294-301
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• 2020

Man-In-Simulant Test(MIST) provides a test method to evaluate chemical protective equipments such as protective garments, gloves, footwear and gas mask. The MIST chamber is built to control concentration of chemical vapor that has a activity space for two persons. Non-toxic methyl-salicylate(MeS) is used to simulate chemical agent vapor. We carried out to measure inward leakage MeS vapors by using passive adsorbent dosimeter(PAD) which are placed on the skin at specific locations of the body while man is activity according to the standard procedure in MIST chamber. But more time is required for PADs and there is concern of contamination in PADs by recovering after experiment. Therefore detector for measuring in real time is necessary. In order to analyze in real time the contamination of the personal protective equipment inside the chemical environment, we have developed a wireless real-time gas detector. The detector consists of 8 gas-sensors and 1 control-board. The control-board includes a CPU for processing a signal, a power supply unit for biasing the sensor and Bluetooth-chipset for transmission of signals to external PC. All signals from gas-sensors are converted into digital signals simultaneously in the control-board. These digital signals are stored in external PC via Bluetooth wireless communication. The experiment is performed by using protective equipment worn on manikin. The detector is mounted inside protective equipment which is capable of providing a real-time monitoring inward leakage MeS vapor. Developed detector is demonstrated the feasibility as real-time detector for MIST.

• Progress in Superconductivity and Cryogenics
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• v.19 no.3
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• pp.44-48
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• 2017

Current lead is a device that connects the power supply and superconducting magnets. High temperature superconductor (HTS) has lower thermal conductivity and higher current density than normal metal. For these reasons, the heat load can be reduced by replacing the normal metal of the current lead with the HTS. Conventional HTS current lead has same cross-sectional area in the axial direction. However, this is over-designed at the cold-end (4.2 K) in terms of current. The heat load can be reduced by reducing this part because the heat load is proportional to the cross-sectional area. Therefore, in this paper, heat load was calculated from the heat diffusion equation of HTS current leads with uniform and non-uniform cross-sectional areas. The cross-sectional area of the warm-end (65K) is designed considering burnout time when cooling system failure occurs. In cold-end, Joule heat and heat load due to current conduction occurs at the same time, so the cross-sectional area where the sum of the two heat is minimum is obtained. As a result of simulation, current leads for KSTAR TF coils with uniform and non-uniform cross-sectional areas were designed, and it was confirmed that the non-uniform cross-sectional areas could further reduce the heat load.

• The Journal of the Acoustical Society of Korea
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• v.33 no.2
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• pp.111-117
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• 2014

In this paper, the structure-borne noise reduction on electrical equipment is discussed by the experimental analysis. The water cooling system in electrical equipment is the only noise source, so the mock-up was made to measure noise characteristics. Effects of power supply, stiffness, isolation of noise source and natural frequency determined by resilient mounts are investigated using the mock-up. The console prototype was made referring to noise reduction technique by the mock-up. The structure-borne noise level of a console prototype was measured and some experiments to reduce the noise was undertaken. The $1^{st}$ and $4^{th}$ harmonics of operating frequency of cooling fans causes highest structure-borne noise levels. The control of operating speeds of several DC cooling fan groups was tried. Also types and installation layouts of resilient mounts were investigated. To reduce structure-borne noise, followings can be applied: increase of stiffness, isolation of source, decrease of natural frequency of mount, combination of operating speed of fans, selection of mounts, and so on.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.19 no.9
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• pp.615-621
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• 2007

Experimental study on the heat transfer characteristics of $CO_2$ in a horizontal smooth tube was carried out to investigate the heat transfer coefficient and pressure drop during evaporation of $CO_2$. The experiment apparatus consisted of a test section, a DC power supply, a heater, a chiller, a mass flow meter, a pump and a measurement system. Experiment was conducted for various mass fluxes ($200{\sim}1200kg/m^2s$), heat flukes ($10{\sim}100kW/m^2$) and saturation temperatures (-5, 0, $5^{\circ}C$). With increasing the heat flux, the evaporation heat transfer coefficient increased. But the variation of the heat transfer coefficient on the increase of the mass flux was not large. And the significantly drops of the heat transfer coefficient was observed at any heat flux and mass flux because of the change of the flow pattern in the tube. With increasing the saturation temperature, the heat transfer coefficient increased due to the promotion of a nucleate boiling. The measured pressure drop during evaporation increased with increasing the mass flux and decreasing the saturation temperature.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.21 no.1
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• pp.16-22
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• 2009

In order to investigate $CO_2$ heat transfer coefficient and pressure drop by PAG oil concentration during $CO_2$ evaporation, the experiment on evaporation heat transfer characteristics in a mini-channels were performed. The experimental apparatus consisted of a test section, a DC power supply, a heater, a chiller, a mass flow meter, a pump and a measurement system. Experiment was conducted for various mass fluxes($300{\sim}800kg/m^{2}s$), heat fluxes($10{\sim}40kW/m^2$) saturation temperatures($-5{\sim}5^{\circ}C$), and PAG oil concentration(0, 3, 5wt%). The variation of the heat transfer coefficient was different according to the oil concentration. With the increase of the oil concentration, the evaporation heat transfer coefficient decreased and the delay of dryout by oil addition was found. Pressure drop increased with the increase of the oil concentration and heat flux, and the decrease of saturation temperature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.