• Title/Summary/Keyword: Power Saving Circuit

검색결과 95건 처리시간 0.02초

절전형 전자식 안전기용 LLCC형 공진형 인버터의 특성에 관한 연구 (A Study on the Characteristic of LLCC Type Resonant Inverter for Power Saving Type of Electronic Ballast)

  • 임중열;신일철;서기열;강병복;윤형상;최장균;차인수
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1997년도 전력전자학술대회 논문집
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    • pp.216-221
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    • 1997
  • At present, high frequency electronic ballast are widely used to drive the fluorescent lamp at high frequency for improving light quality. The electronic ballast mainly consist of an inverter stage with a load resonant circuit. This paper derives a lamp model consist of a voltage equation and a current equation. The proposed model is useful for an engineer to determine circuits and to analyze the performance of electronic ballast with high frequency operation. Simulation with PSPICE and experimentator and the high power factor of the proposed topology.

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Single-Scan Plasma Display Panel(PDP)를 위한 고속 어드레스 에너지 회수 기법 (A High Speed Address Recovery Technique for Single-Scan Plasma Display Panel(PDP))

  • 이준용
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제54권9호
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    • pp.450-453
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    • 2005
  • A high speed address recovery technique for AC plasma display panel(PDP) is proposed. Replacing GND switch by clamping diode. the recovery speed can be increased by saving GND hold-time and switching loss due to GND switch also becomes also be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Test results with 50' HD single-scan PDP(resolution = 1366$\times$768) show that less than 3sons of recovery time is successfully accomplished and about$54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.

Design, Analysis, and Equivalent Circuit Modeling of Dual Band PIFA Using a Stub for Performance Enhancement

  • Yousaf, Jawad;Jung, Hojin;Kim, Kwangho;Nah, Wansoo
    • Journal of electromagnetic engineering and science
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    • 제16권3호
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    • pp.169-181
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    • 2016
  • This work presents a new method for enhancing the performance of a dual band Planer Inverted-F Antenna (PIFA) and its lumped equivalent circuit formulation. The performance of a PIFA in terms of return loss, bandwidth, gain, and efficiency is improved with the addition of the proposed open stub in the radiating element of the PIFA without disturbing the operating resonance frequencies of the antenna. In specific cases, various simulated and fabricated PIFA models illustrate that the return loss, bandwidth, gain, and efficiency values of antennas with longer optimum open stub lengths can be enhanced up to 4.6 dB, 17%, 1.8 dBi, and 12.4% respectively, when compared with models that do not have open stubs. The proposed open stub is small and does not interfere with the surrounding active modules; therefore, this method is extremely attractive from a practical implementation point of view. The second presented work is a simple procedure for the development of a lumped equivalent circuit model of a dual band PIFA using the rational approximation of its frequency domain response. In this method, the PIFA's measured frequency response is approximated to a rational function using a vector fitting technique and then electrical circuit parameters are extracted from it. The measured results show good agreement with the electrical circuit results. A correlation study between circuit elements and physical open stub lengths in various antenna models is also discussed in detail; this information could be useful for the enhancement of the performance of a PIFA as well as for its systematic design. The computed radiated power obtained using the electrical model is in agreement with the radiated power results obtained through the full wave electromagnetic simulations of the antenna models. The presented approach offers the advantage of saving computation time for full wave EM simulations. In addition, the electrical circuit depicting almost perfect characteristics for return loss and radiated power can be shared with antenna users without sharing the actual antenna structure in cases involving confidentiality limitations.

피에조 액츄에이터 구동용 에너지 회수형 인버터의 특성과 구동 기법 연구 (A Study on Characteristics and Driving Techniques of Energy Recovery Type Inverter for Piezo Actuator Drive)

  • 홍선기;이정섭;변남희;나유청;강태삼
    • 전기학회논문지
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    • 제62권8호
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    • pp.1095-1100
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    • 2013
  • Piezo devices have large power density and simple structure compared with conventional electrical motors. Thus they can generate larger forces than the conventional actuators with small size. Their resopnses to commands are also very fast and thus the bandwidths are very wide. Thus the piezo devices are expected to be used widely in the future for actuating devices requiring fast response and large actuating force with small size. However, the piezo actuators need high voltage with high driving current due to their large capacitive property. In this paper, proposed is a simple method to drive piezo devices using voltage inversion circuit with coli inductance. The coil inductance carries the charges in the piezo device to the opposite side, inverting the polarity of the applied voltage, thus saving the power to drive the device with AC voltages. Experiments with real circuit demonstrates that the proposed scheme can improve the energy efficiency very much.

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

  • Truong, Son Ngoc;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권3호
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    • pp.356-363
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    • 2014
  • In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

소형전원장치에 대한 통계적 분석 (Statistical analysis for small power module)

  • 신재경
    • Journal of the Korean Data and Information Science Society
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    • 제22권4호
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    • pp.735-740
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    • 2011
  • 최근 전자기기의 소형화, 인텔리전트화, 다기능화, 광대역화에 관심이 집중되어 많은 발전이 이루어졌으며, 이들 전자기기들에 이용되는 모듈형의 전원장치 (SMPS : Switching-mode power supply)도 소형화, 경량화, 고효율화, 고신뢰성화, 저노이즈화를 실현하고 있다. 85~265 볼트교류전압(VAC : Voltage alternating current) 상용 전원을 공급받아 DC 출력을 공급하는 전원장치인 파워모듈은 마이크로컨트롤러, 릴레이 등 전기, 전자 회로용 전원 공급기를 간단하고 쉽게 설계하도록 개발되고 있다. 이 모듈은 전원을 사용하는 장비에 광범위하게 적용할 수 있어 에너지 절감이라는 세계적인 대과제에 적합한 제품이기는 하나 제품의 품질과 성능에 대한 통계적분석이 필요한 바 적용제품의 부하별, 출력전압별 성능분석을 하여 그 문제점을 찾아보려고 한다.

오류 정정기능이 내장된 6-비트 70MHz 새로운 Interpolation-2 Flash ADC 설계 (A 6-bit, 70MHz Modified Interpolation-2 Flash ADC with an Error Correction Circuit)

  • 박정주;조경록
    • 대한전자공학회논문지SD
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    • 제41권3호
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    • pp.83-92
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    • 2004
  • 본 논문에서는 새로운 interpolation-2 방식의 비교기 구조를 제안하여 칩 면적과 전력 소모를 줄이며 오류정정 회로를 내장하는 6-비트 70㎒ ADC를 설계하였다. Interpolation 비교기를 적용하지 않은 flash ADC의 경우 2n개의 저항과 2n -1개의 비교기가 사용되며 이는 저항의 수와 비교기의 수에 비례하여 많은 전력과 큰 면적을 필요로 하고 있다. 또한, interpolation-4 비교기를 적용한 flash ADC는 면적은 작으나 단조도, SNR, INL, DNL 특성이 떨어진다는 단점이 있었다. 본 논문에서 설계한 interpolation-2 방식의 ADC는 저항, 비교기, 앰프, 래치, 오류정정 회로, 온도계코드 디텍터와 인코더로 구성되며, 32개의 저항과 31개의 비교기를 사용하였다. 제안된 회로는 0.18㎛ CMOS 공정으로 제작되어 3.3V에서 40mW의 전력소모로 interpolation 비교기를 적용하지 않은 flash ADC에 비해 50% 개선되었으며, 칩 면적도 20% 감소되었다. 또한 노이즈에 강한 오류정정 회로가 사용되어 interpolation-4 비교기를 적용한 flash ADC 에 비해 SNR이 75% 개선된 결과를 얻었다.

Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder

  • Guduri, Manisha;Islam, Aminul
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.302-317
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    • 2017
  • This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

전력선 통신기술을 이용한 조명제어 스위치의 개발 (Development of a Lighting Control Switch Using Power Line Communication Technology)

  • 길경석;송재용;문승보;이경수;김창율
    • 한국정보통신학회논문지
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    • 제9권4호
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    • pp.792-797
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    • 2005
  • 본 논문에서는 전력선 통신과 조광 기술을 기반으로 에너지 절약과 적정 조도의 제어가 가능한 조명제어 스위치의 개발에 대하여 기술하였다. 개발된 스위치는 범용의 마이크로프로세서와 주변 전자기술을 이용하며, 하나의 마이크로프로세서로 전력선 통신과 조광기능을 구현함으로서 저가격 상용화가 가능하였다. 캐리어 주파수는 전송 데이터 길이와 신호감쇄를 고려하여 250kHz로 설정하였다. 저압선로에서 시제작품에 대한 시험결과, 본 스위치는 전력선의 길이와 부하용량의 변동에 대해 강인하게 동작하는 것을 확인하였다.

승강장 스크린 도어(PSD)에 대한 고 신뢰성의 감시 및 제어 시스템 개발 (Development of High Reliability Monitoring and Control System for Platform Screen Door)

  • 김진식;손진근
    • 전기학회논문지P
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    • 제59권2호
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    • pp.158-162
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    • 2010
  • PSD is automatically opened and closed when subway train arrive on the station. This system was designed to control electric automatic system. These doors will provide passenger safety, energy saving and a good environment in subway. The monitoring and control systems of PSD are configured so that they can be operated in automatic mode in connection with ATO through the composite control panel in the station control room. The objective of this paper is to obtain high reliability that is essential for monitoring and control systems of PSD. The power supply is based on protection circuit using DC power bridge from two UPS. Also, stable communication system consists of CAN communication line redundancy and RF cross protection algorithm. Monitoring state display results show the validity of the proposed high reliability monitoring and control systems of PSD.