• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

• Nuclear Engineering and Technology
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• v.21 no.4
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• pp.294-301
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• 1989

The Axial Power Distribution Monitoring System(APDMS) program was developed to calculate a detailed axial power distribution using two-level excore detector, cold leg temperature and control rod position signals. The unnormalized two-level excore detector signals were corrected for the rod shadowing factor determined by control rod position and for the temperature shadowing factor calculated based on cold leg temperature. A shape annealing matrix was then applied to the corrected excore detector response to yield peripheral power. After the core average power was obtained using linear relationship bet-ween core average and peripheral power, the boundary point power correction coefficient was applied to core average power in order to obtain boundary power for both upper and lower core axial boundaries. Then, the axial power distribution was synthesized by spline approximation. In spite of burnup, power level, control rod postion and axial offset changes, the comparisons of axial power distributions between BOXER simulation program and APDMS results showed good agreements within 5% root mean square error for Kori Unit 3 Cycle 4.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.128-134
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• 2010

In this paper, a high-power 20-way stripline power divider with low insertion loss and low side lobe level is successfully designed, fabricated and measured as a feed network for an S-band linear array antenna having Dolph-Chebyshev current distribution which has a narrow beam width and very low side lobe level (SLL). The 20-way stripline power divider consists of an 8-way power divider, three 4-way power dividers and three ring hybrids. It utilizes a T-junction structure as a basic element for power dividing. Notches and modified input/output N-to-stripline transitions are used for improving insertion loss and return loss. The fabricated power divider shows insertion loss less than 0.3 ㏈ and rms phase mismatch less than 8o in the full bandwidth. A final 40-way power divider is synthesized by combining symmetrically two 20-way power dividers and is expected to have SLL over 40 dB, based on the measured results of the 20-way power divider.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.1-6
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• 2008

In this paper, bias control circuit structure have been employed to improve the power added efficiency of the CMOS class-E power amplifier on low input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal. The proposed CMOS class-E power amplifier using bias controlled circuit has been improved the PAE on low output power level. The operating frequency is 2.14GHz and the output power is 22dBm to 25dBm. In addition to, it has been evident that the designed the structure has showed more than a 80% increase in PAE for flatness over all input power level, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.159-163
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• 2004

We have introduced fourth generation PDPs last year. The performance of these PDPs is the highest level among TV displays. At the same time the power consumption of them has reached to the lowest level among FPDs (Flat Panel Displays). High panel luminous efficacy and low address power are necessary for the reduction of total power consumption. Following technologies have been developed and applied to the fourth generation PDPs. High panel luminous efficacy: T-shape electrode, waffle rib structure, high Xe content gas Low address power; CLEAR driving method, etc.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.343-344
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• 2016

This paper is presents a design of high voltage level rectifier converter in SST(Solid state transformer). Also verify the converter through simulation and experiment.

• Journal of Power Electronics
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• v.18 no.2
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• pp.407-417
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• 2018

A novel family of Buck mode three-level direct ac converters with a high frequency link is proposed. These converters can transfer an unsteady high ac voltage with distortion into a regulated sinusoidal voltage with a low THD at the same frequency. The circuit configuration is constituted of a three-level converter, high frequency transformer, cycloconverter, as well as input and output filters. The topological family includes forward, push-pull, half-bridge, and full-bridge modes. In order to achieve a reliable three-level ac-ac conversion, and to overcome the surge voltage and surge current of the cycloconverter, a phase-shifted control strategy is introduced in this paper. A prototype is presented with experimental results to demonstrate that the proposed converters have five advantages including high frequency electrical isolation, lower voltage stress of the power switches, bi-directional power flow, low THD of the output voltage, and a higher input power factor.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.319-328
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• 2020

The recent use of distributed power generation systems constructed with DC-DC converters has become extremely popular owing to the rising need for environment friendly energy generation power systems. In this study, a new single-phase five-level inverter for off-grid applications constructed with a multilevel DC-DC step-up converter is proposed to boost a low-level DC voltage (36 V-64 V) to a high-level DC bus (380 V) and invert and connect them with a single-phase 230 V rms AC load. Compared with other traditional multilevel inverters, the proposed five-level inverter has a reduced number of switching devices, can generate high-quality power with lower THD values, and has balanced voltage stress for DC capacitors. Moreover, the proposed topology does not require multiple DC sources. Finally, the performance of the proposed topology is presented through the simulation and experimental results of a 400 W hardware prototype.

• Journal of the Society of Naval Architects of Korea
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• v.56 no.6
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• pp.497-506
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• 2019

Literature survey was conducted on the 2013 Interim Guidelines for determining the minimum propulsion power to maintain the manoeuvrability of ships in adverse conditions. The International Maritime Organization (IMO) Marine Environment Protection Committee (MEPC) documents related with the Guidelines were reviewed. Compatibility of the present Guidelines can be checked by two different levels: (Level 1) minimum power lines assessment and (Level 2) simplified assessment. The IHS (Information Handling Services) sea-web data on the bulk carriers and the tankers, which were built after 2000, were used to examine the Level 1 assessment. KVLCC2 was used to examine the Level 2 assessment. Regarding the Level 2 assessment, effects of the adverse weather conditions, the added resistance due to waves, the wake fractions and the thrust deduction factors were discussed.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.197-198
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• 2015

본 논문은 에너지저장(ESS : Energy Storage System) 기능을 갖는 500kVA급 3-Level 하이브리드 무정전전원장치(UPS : Uninterruptible Power Supply)에 관한 것으로 평상시 무정전 전원장치의 기능을 수행하다 전력 부족시 또는 첨두부하시 에너지저장 기능을 제공하는 기술에 대한 내용이다. 실험을 통하여 제안한 시스템의 우수성을 검증한다.