• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.719-726
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• 2008

In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1234-1245
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• 2018

The risk of multi-unit nuclear power plants (NPPs) at a site has received considerable critical attention recently. However, current probabilistic safety assessment (PSA) procedures and computer code do not support multi-unit PSA because the traditional PSA structure is mostly used for the quantification of single-unit NPP risk. In this study, the main purpose is to develop a multi-unit Level 2 PSA method and apply it to full-power operating six-unit OPR1000. Multi-unit Level 2 PSA method consists of three steps: (1) development of single-unit Level 2 PSA; (2) extracting the mapping data from plant damage state to source term category; and (3) combining multi-unit Level 1 PSA results and mapping fractions. By applying developed multi-unit Level 2 PSA method into six-unit OPR1000, site containment failure probabilities in case of loss of ultimate heat sink, loss of off-site power, tsunami, and seismic event were quantified.

• Journal of Power Electronics
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• v.13 no.2
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• pp.177-185
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• 2013

This paper studies a soft switching DC/DC converter to achieve zero voltage switching (ZVS) for all switches under a wide range of load condition and input voltage. Two three-level PWM circuits with the same power switches are adopted to reduce the voltage stress of MOSFETs at $V_{in}/2$ and achieve load current sharing. Thus, the current stress and power rating of power semiconductors at the secondary side are reduced. The series-connected transformers are adopted in each three-level circuit. Each transformer can be operated as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer from the input side to the output side. Therefore, no output inductor is needed at the secondary side. Two center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Due to the resonant behavior by the resonant inductance and resonant capacitance at the transition interval, all switches are turned on at ZVS. Experiments based on a 1kW prototype are provided to verify the performance of proposed converter.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.2
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• pp.50-54
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• 2009

In this paper, we address a novel system-level power management technique which is specifically targeted for an ARM 11 MPCore system. Our proposed solution is a DPM technique which includes process monitoring, real time power analysis, and policy application to reduce the power consumption while meeting the performance requirement. One of the main contributions of this paper is that we systematically infer QoS requirements of processes without getting any additional information from the application. When multiple processes are running under various user level policies, priorities of the policy application are determined in such a way that the overall system performance is maintained while power consumption is effectively managed. Experimental results show that our DPM technique is very effective in reducing power consumption without violating system's QoS requirements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1167-1176
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• 1995

This paper suggests a method for optimal power assignment of the satellite transponder input carriers in the Multi-level & Multi-bandwidth system. The interference and the noise effects analyzed for the optimal power assignment are intermodulation product caused by the nonlinear transponder characteristics, adjacent channel interference, co-channel interference, and thermal noise in the satellite link. The Fletcher- Powell algorithm is used to determine the optimal input carrier power. The performance criteria for optimal power assignment is classified into 4 categories according to the CNR of destination receiver earth station to meet the requirement for various satellite link environment. We have performed mathematical analysis of objective functions and their derivatives for use in the Fletcher-Powell algorithm, and presented various simulation results based on mathematical analysis. Since the satellite link, it is meaningful to model and analyze these effects in a unified manner and present the method for optimal power assignment of transponder input carriers.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.384-386
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• 2006

본 논문에서는 AC Plasma display panel(AC-PDP) 구동을 위한 Six-switch를 적용한 Three-level PDP Sustain 회로를 제안한다. 제안 회로는 기존 회로의 Sustain 스위치와 Clamp 다이오드의 내압이 절반이 되어 특성이 우수한 반도체 소자의 채택이 가능하며, 환류 전류가 저감되어 높은 전력 효율을 가지는 장점을 가지므로 AC-PDP 구동 회로 설계에 매우 적합하다. 본 논문에서는 기존 회로와 제안 회로의 전도 손실 계산 및 시뮬레이션과 실험 결과를 보였다.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1160-1172
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• 2017

A novel space vector modulation strategy in the non-orthogonal three-dimensional coordinate system for multi-level three-phase four-wire inverters is proposed in this paper. This new non-orthogonal three-dimensional space vector modulation converts original trigonometric functions in the orthogonal three-dimensional space coordinate into simple algebraic operations, which greatly reduces the algorithm complexity of three-dimensional space vector modulation and preserves the independent control of the zero-sequence component. Experimental results have verified the correctness and effectiveness of the proposed three-dimensional space vector modulation in the new non-orthogonal three-dimensional coordinate system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.7
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• pp.380-388
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• 2006

In this paper, a novel control algorithm to minimize the power loss of the induction generator for wind power generation system is presented. The proposed method is based on the flux level reduction, where the flux level is computed from the machine model for the optimum d-axis current of the generator. For the vector-controlled induction generator, the d-axis current controls the excitation level in order to minimize the generator loss while the q-axis current controls the generator torque, by which the speed of the induction generator is controlled according to the variation of the wind speed in order to produce the maximum output power. Wind turbine simulator has been implemented in laboratory to validate the theoretical development. The experimental results show that the loss minimization process is more effective at low wind speed and that the percent of power loss saving can approach to 25%. Experimental results are shown to verify the validity of the proposed scheme.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.1-10
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• 1997

By considering low power design at higher levels of abstraction rather than at lower levels of abstraction, we can apply various transformation techniques to a system design with wider view and obtain much more effective power reduction with less cost and effort. In this paper, a transformation technique, called power - conscious loop folding is proposed for high level synthesis of a low power system.Our work is focused on reducing the power consumed by functional units in adata path dominated circuit through the decrease of switching activity. Te transformation algorithm has been implemented and integrated into HYPER, a high level synthesis system for experiments. In our experiments, we could achieve a pwoer reduction of up to 50% for data path dominated circuits.