• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.89-96
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• 2015

This paper presents a high efficiency, PSM/DCM/CCM triple mode boost DC-DC converter for mobile application. This device operates at Pulse-Skipping Mode(PSM) when it enters light load, and otherwise operate the operating frequency of 1.4MHz with Pulse-Width Modulation(PWM) mode. Especially in order to improve the efficiency during the Discontinuous-Conduction Mode(DCM) operation period, the reverse current prevention circuit and oscillations caused by the inductor and the parasitic capacitor to prevent the Ringing killer circuit is added. The input voltage of the boost converter ranges from 2.5V ~ 4.2V and it generates the output of 4.8V. The measurement results show that the boost converter provides a peak efficiency of 92% on CCM and 87% on DCM. And an efficiency-improving PWM operation raises the efficiency drop because of transition from PWM to PFM. The converter has been fabricated with a 0.18um Dongbu BCDMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• Composites Research
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• v.13 no.5
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• pp.50-59
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• 2000

In this paper, two methods to suppress flutter of the composite panel are examined. First, in the active control method, a controller based on the linear optimal control theory is designed and control input voltage is applied on the actuators and a PZT is used as actuator. Second, a new technique, passive suppression scheme, is suggested for suppression of the nonlinear panel flutter. In the passive suppression scheme, a shunt circuit which consists of inductor-resistor is used to increase damping of the system and as a result the flutter can be attenuated. A passive damping technology, which is believed to be more robust suppression system in practical operation, requires very little or no electrical power and additional apparatuses such as sensor system and controller are not needed. To achieve the great actuating force/damping effect, the optimal shape and location of the actuators are determined by using genetic algorithms. The governing equations are derived by using extended Hamilton's principle. They are based on the nonlinear von Karman strain-displacement relationship for the panel structure and quasi-steady first-order piston theory for the supersonic airflow. The discretized finite element equations are obtained by using 4-node conforming plate element. A modal reduction is performed to the finite element equations in order to suppress the panel flutter effectively and nonlinear-coupled modal equations are obtained. Numerical suppression results, which are based on the reduced nonlinear modal equations, are presented in time domain by using Newmark nonlinear time integration method.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1069-1074
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• 2020

Since DC has no zero point, an arc occurs when the DC circuit breaker performs a shutdown operation. In this case, a fatal accident may occur in the circuit breaker or in the grid, depending on the magnitude of the arc. Therefore, the shutdown performance and the reliability of the circuit breaker are important in the commercialization of HVDC. In this study, a superconducting LC circuit breaker was proposed to improve the performance and the reliability of the DC circuit breaker. The superconducting LC circuit breaker applied a superconducting coil to the inductor of the existing LC circuit breaker. Other than limiting the initial fault current, it also creates a stable zero point in the event of a fault current. To verify this, simulation was performed through EMTDC/PSCAD. Furthermore, the superconducting LC circuit breaker was compared with the LC circuit breaker with a normal coil. As a result, it was found that the LC circuit breaker with the superconducting coil limited the initial fault current further by approximately 12 kA compared to the LC circuit breaker with a normal coil. This reduced the arc extinguish time by approximately 0.16 sec, thereby decreasing the elctrical power burden on the circuit breaker.