• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10a
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• pp.414-418
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• 2006

유비쿼터스 컴퓨팅의 인프라가 되는 센서 네트워크는 매우 작은 하드웨어로 이루어지는 많은 수의 센서 노드들로 구성된다. 이 네트워크의 토폴로지와 라우팅 방식은 그 목적에 따라 결정되어야 하며, 하드웨어 및 소프트웨어도 필요한 경우에는 변경되어야 한다. 따라서 그러한 네트워크를 최적으로 설계하기 위해서는 시스템 동작을 확인하고 성능을 예측할 수 있는 센서 네트워크 시뮬레이터가 필요하다. 현존하는 몇몇 센서 네트워크 시뮬레이터들은 특정 하드웨어나 운영체제에 맞추어 개발되었기 때문에, 그러한 특정 시스템들을 위해서만 사용될 수 있다. 그리고 시스템 설계 상의 주요 이슈가 되는 전력 소모량 및 프로그램 실행 시간을 추정하기 위한 어떤 수단도 지원하지 못하고 있다. 이 연구에서는 기존의 센서 네트워크 시뮬레이터들이 갖고 있는 문제점을 해결한 시뮬레이터를 개발하고, 센서 네트워크의 계층적 라우팅 프로토콜인 LEACH, TEEN, APTEEN의 전력소모량을 시뮬레이션을 이용하여 분석하였다. 시뮬레이션의 작업부하인 명령어 트레이스로는 ATmega128L 마이크로컨트롤러용 크로스컴파일러에 의해 생성된 실행 이미지를 사용하였다. 따라서 각각의 라우팅 프로토콜을 실제 센서 보드에서 동작하는 응용 프로그램으로 구현하고, 컴파일된 실행 이미지를 작업부하로 사용하여 시뮬레이션 하였다. 라우팅 프로그램들은 ETRI의 센서 네트워크 운영체제인 Nano-Q+ 1.6.1을 기반으로 구현되었으며, 하드웨어 플랫폼은 옥타컴의 센서 보드인 Nano-24이다. 시뮬레이션 결과에 따르면, 센서 네트워크는 그 사용 목적에 따라 라우팅 프로토콜을 적절히 선택해야 한다는 것을 알 수 있다. 즉, LEACH는 주기적으로 네트워크의 상황을 체크해야 하는 경우에 적합하고, TEEN은 환경의 변화를 수시로 감지해야 하는 경우에 적합하다. 그리고 APTEEN은 전력소모량과 기능 측면을 모두 고려할 때 가장 효과적인 라우팅 프로토콜이라고 할 수 있다.iRNA 상의 의존관계를 분석할 수 있었다.수안보 등 지역에서 나타난다 이러한 이상대 주변에는 대개 온천이 발달되어 있었거나 새로 개발되어 있는 곳이다. 온천에 이용하고 있는 시추공의 자료는 배제하였으나 온천이응으로 직접적으로 영향을 받지 않은 시추공의 자료는 사용하였다 이러한 온천 주변 지역이라 하더라도 실제는 온천의 pumping 으로 인한 대류현상으로 주변 일대의 온도를 올려놓았기 때문에 비교적 높은 지열류량 값을 보인다. 한편 한반도 남동부 일대는 이번 추가된 자료에 의해 새로운 지열류량 분포 변화가 나타났다 강원 북부 오색온천지역 부근에서 높은 지열류량 분포를 보이며 또한 우리나라 대단층 중의 하나인 양산단층과 같은 방향으로 발달한 밀양단층, 모량단층, 동래단층 등 주변부로 NNE-SSW 방향의 지열류량 이상대가 발달한다. 이것으로 볼 때 지열류량은 지질구조와 무관하지 않음을 파악할 수 있다. 특히 이러한 단층대 주변은 지열수의 순환이 깊은 심도까지 가능하므로 이러한 대류현상으로 지표부근까지 높은 지온 전달이 되어 나타나는 것으로 판단된다.의 안정된 방사성표지효율을 보였다. $^{99m}Tc$-transferrin을 이용한 감염영상을 성공적으로 얻을 수 있었으며, $^{67}Ga$-citrate 영상과 비교하여 더 빠른 시간 안에 우수한 영상을 얻을 수 있었다. 그러므로 $^{99m}Tc$-transierrin이 감염 병소의 영상진단에 사용될 수 있을 것으로 기대된다.리를 정량화 하였다. 특히 선조체에서의 도파민 유리에 의한 수용체 결합능의 감소는 흡연에 의한 혈중 니코틴의 축적 농도와 양의 상관관계를 보였다(rho=0.9, p=0.04). 결론: $[^{11}C]raclopride$ PET을 이용하여 비흡연 정상인에서 흡연에 의한 도파민 유리를 영상화 및 정량화 하였고, 흡연에 의한 선조체내 도파민 유리는 흡연시 흡수된

• Journal of KIISE:Information Networking
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• v.36 no.4
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• pp.339-350
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• 2009

In wireless sensor networks, the limited battery resources of sensor nodes have a direct impact on network lifetime. To reduce unnecessary power consumption, it is often the case that only a minimum number of sensor nodes operate in active mode while the others are kept in sleep mode. In such a case, however, the network service can be easily unreliable if any active node is unable to perform its sensing or communication function because of an unexpected failure. Thus, for achieving reliable sensing, it is important to maintain the sensing level even when some sensor nodes fail. In this paper, we propose a new fault-tolerance scheme, called FCP(Fault-tolerant Coverage Preserving), that gives an efficient way to handle the degradation of the sensing level caused by sensor node failures. In the proposed FCP scheme, a set of backup nodes are pre-designated for each active node to be used to replace the active node in case of its failure. Experimental results show that the FCP scheme provides enhanced performance with reduced overhead in terms of sensing coverage preserving, the number of backup nodes and the amount of control messages. On the average, the percentage of coverage preserving is improved by 87.2% while the additional number of backup nodes and the additional amount of control messages are reduced by 57.6% and 99.5%, respectively, compared with previous fault-tolerance schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.879-886
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• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• The Journal of Korean Institute of Information Technology
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• v.15 no.12
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• pp.157-164
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• 2017

Mobile ECG signal measurement is a technique to measure small signals of several mV, and many studies have been conducted to remove noise including wandering scheme. Removal of the equipotential line noise caused by shaking or movement of the electrode cable is one of the core research contents for the electrocardiogram measurement. In this study, we proposed a modified step-size of combined NLMS(normalized least squares) and DLMS(delayed least squares) adaptive filter to eliminate baseline noise from ECG signals. The proposed method mainly adjusts initial filter step-size to reduce distortion of original ECG signals characteristic after eliminating baseline noise. The modified filter step-size is scaled by filter order size and distortion minimization factor. This method is suitable for portable ECG device with a small processor and less power consumption. This technique also decreases computation time which is essential for real-time filtering. The proposed filter also increase the signal to noise ratio (SNR) compared to conventional NLMS filter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.282-289
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• 2019

Reflective and solar LED road studs are being used as a way of securing visibility for road environments. Road markers have various advantages and disadvantages in terms of versatility, efficiency, simplicity and visibility as individual products of reflective type and solar LED. However, in addition to the above, it is possible to prevent secondary accident after accident, It has a common drawback that it is difficult to have. In this paper, we propose a road stud system incorporating a wireless control function using RF - based communication with existing solar LED road studs and a system for controlling them. The proposed system is called the smart road stud system and it can control the equipment through the central control unit and the relay unit connected to the central control room by incorporating the RF communication function in the existing solar LED road stud. In addition, since it is possible to control the lighting method, color, etc. according to the road condition, it is possible to provide the driver with the state of the road to perform the function for preventing the second accident after the accident. It also adds features that minimize the ongoing power consumption of LED and RF communications. In order to verify the validity of the proposed system, prototypes were produced and it was confirmed that it is possible to act as a university for prevention of accident after accident by linking with other traffic system besides accident prevention function by securing existing visibility.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.565-568
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• 2014

This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.