Drain Induced Barrier Lowering(DIBL) SPICE Model for Sub-10 nm Low Doped Double Gate MOSFET (10 nm 이하 저도핑 DGMOSFET의 SPICE용 DIBL 모델)
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- Journal of the Korea Institute of Information and Communication Engineering
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- v.21 no.8
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- pp.1465-1470
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- 2017