• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.113-117
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• 2003

The digital systems include the noise in power supply, ground and packaging due to a simultaneous switching of signal, signal reflections and distortions on single and multiple transmission lines. The requirement for the controlled impedance on a PCB can be both a critical success factor and a design challenge. So, the invented tool simulates the tracks controlled impedance with the test coupon. It can saves the design time and supports the economical PCB design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.149-153
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• 1999

As VLSI technology advances rapidly, the operating frequency of digital systems becomes very fast. In such a high-speed system, there are many factors that threaten signal integrity. The noise sources in digital system include the noises in power supply, ground bounce and packaging media and distortions on single and multiple transmission lines. This paper will present a technology survey useful in the design of Gigabit interconnection systems. Some case studies have been constructed which show the lossy transmission line effect of skin effect. dielectric loss, with backplane connectors using the theoretical and practical conditions.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 E
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• pp.1592-1595
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• 1998

The rock fragmentation system with a capacitor bank, switching device, cable and blasting electrode are described. Utilization of the chemical energy from the electrolyte and the pseudospark with a large current capacity suggested the commercialization possibility of the rock fragmentation system. The vibration and noise level of the pulsed blasting is acceptable in the most ground breaking. And also the electromagnetic force produced by the inductor is introduced for the rock fragmentation.

• 한국음향학회지
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• 제31권5호
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• pp.309-316
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• 2012

본 논문에서는 다중 전압을 사용하는 초소형 시스템 구성 및 모듈 설계 방법론을 제시한다. 특히 잡음에 취약한 아날로그 IC의 특성을 개선하기 위한 PDN 구성 방법과 필터 구성 방법에 중점을 두어 설계하였다. 이에 제작된 모듈은 고전압에 의한 잡음을 방지하기 위해 공급 전원별로 접지면을 분할하고, 이를 공통 접지면으로 구성하기 위해 필터를 연결하였으며, via stitching 기법을 사용하였다. 이를 본 논문에서는 PDN 구조를 Lumped 모델로 구성하여 시뮬레이션을 통해 분석하고, 측정을 통해 확인하였다. 시뮬레이션 결과 4.7 uH의 Inductor를 연결하였을 때, 공통 접지면을 사용했을 때보다 -7 dB의 잡음 감소 효과를 확인할 수 있었고, 측정 결과 약 12 %가 감소하였음을 확인할 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.497-500
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• 2001

Shunt reactors are used to compensate for capacitive VARs generated by lightly loaded transmission lines or underground cables. They are normally connected to the transformer tertiary winding. Dry-type shunt reactors have the advantage compared with oil-immersed shunt reactor as followings. Lower investment and maintenance cost, No fire hazard and no environmental concerns, Simple insulation to ground, Response to transient overvoltage less severe, Linearity of inductance versus load current, Lower-acoustic noise, Easier transport and handling due to lower weight, No oil-collecting system must be provided since there is no oil that can leak into the ground.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권5호
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• pp.245-249
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• 2006

Corona characteristics of conductors are dependent on the electric field conditions in the immediate vicinity of the conductors. In case of DC transmission line, particularly, the space charge plays an important role in the electric field distribution. Therefore, DC corona cage simulation is necessary for long-term test in the same conditions. This paper presents the results of designing and constructing hardwares such as DC power supply, measurement system and DAS to carry out the simulation. The corona cage longitudinally is divided into five equal length sections and three inner sections of those are isolated from the ground of outer cage. The measurement items are radio noise, corona current, television noise, audible noise and meteorological conditions. In the next step, various simulations about the type and configuration of two or three candidate conductors will be conducted. And then finally an environmentally-friendly conductor for HVDC overhead transmission line will be decided.

• 한국지진공학회논문집
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• 제23권6호
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• pp.321-327
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• 2019

We performed seismic noise level analysis to access the proper functioning of 11 newly established seismic stations in the southeastern region of Korea. One-hour long segments of seismograms were selected from the continuous data of the 3 elements for 61 days from March 1, 2019. For each segment of data, the power spectral density (PSD) was estimated from the continuous back ground noise data of the 3 elements for periods ranging from 0.02~100 s. The median noise levels (NLs) of the stations were compared with the new noise model (NNM) of USGS and NLs of station TJN installed in a tunnel on a granite basement. We observed that the NLs of the newly installed seismometers were between the upper and lower limit of the NNM. In a comparison with the noise level of station TJN, the new seismometers had their own noteworthy features. The NLs from accelerometers (Epi-sensors) were ~ 40 dB higher than the NLs from velocimeters (STS-sensors) for periods > 10 s, which is because the small and light Epi-sensors are sensitive to environmental changes. Daily and weekly variations in spectral noise level were observed clearly in short periods < 1 s, and these are considered to be related to human activities. The seismometers in boreholes showed ~20 dB weaker NLs in the cultural noise band. The NLs of accelerometers at a depth of 30 m were also much lower by 30 dB for long periods > 10 sec. Overall the functioning of the new velocimeter and accelerometer stations was reliable for periods ranging from 0.02~100 s and 0.02~10 s, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.279-282
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• 2000

As digital systems continue to use components with faster edge rates and clock speeds, transmission of the digital information in these systems approaches the microwave realm. At these speeds digital signal fidelity becomes both a critical success factor and design challenge. The noise sources in digital systems include the noise in power supply, ground and packaging media due to simultaneous switching of drivers, signal reflections and distortions on single and multiple transmission lines. This paper presents theory, case studies and design considerations of gigabit interconnection for network and communication systems. The case studies show HSPICE and Ampredictor simulations of alternate approaches. Various subjects including skin effect and dielectric losses, interconnect simulations and crosstalks of connector, affected signal discontinuity, are addressed.

• Journal of Computing Science and Engineering
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• 제6권4호
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• pp.257-266
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• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.51-54
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• 2002

As digital systems continue to use components with faster edge rate and clock speeds, transmission of the digital information can take place many troubles. The increasing requirement for controlled impedance PCBs becomes both a critical success factor and a design challenge. Especially, the noise sources in digital system include the noise in power supply, ground and packaging due to simultaneous switching of signal, signal reflections and distortions on single and multiple transmission lines. This paper simulates the tracks controlled impedance with the test coupon. So, it can saves the design time and supports the economical PCB design.